xref: /openbmc/u-boot/arch/arm/mach-socfpga/Kconfig (revision 2ca47137)
1if ARCH_SOCFPGA
2
3config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
4	default 0xa2
5
6config TARGET_SOCFPGA_ARRIA5
7	bool
8	select TARGET_SOCFPGA_GEN5
9
10config TARGET_SOCFPGA_ARRIA10
11	bool
12	select ALTERA_SDRAM
13	select SPL_BOARD_INIT if SPL
14	select CLK
15	select SPL_CLK if SPL
16	select DM_I2C
17	select DM_RESET
18	select SPL_DM_RESET if SPL
19	select REGMAP
20	select SPL_REGMAP if SPL
21	select SYSCON
22	select SPL_SYSCON if SPL
23	select ETH_DESIGNWARE_SOCFPGA
24
25config TARGET_SOCFPGA_CYCLONE5
26	bool
27	select TARGET_SOCFPGA_GEN5
28
29config TARGET_SOCFPGA_GEN5
30	bool
31	select ALTERA_SDRAM
32
33config TARGET_SOCFPGA_STRATIX10
34	bool
35	select ARMV8_MULTIENTRY
36	select ARMV8_SET_SMPEN
37	select ARMV8_SPIN_TABLE
38	select FPGA_STRATIX10
39
40choice
41	prompt "Altera SOCFPGA board select"
42	optional
43
44config TARGET_SOCFPGA_ARRIA10_SOCDK
45	bool "Altera SOCFPGA SoCDK (Arria 10)"
46	select TARGET_SOCFPGA_ARRIA10
47
48config TARGET_SOCFPGA_ARRIA5_SOCDK
49	bool "Altera SOCFPGA SoCDK (Arria V)"
50	select TARGET_SOCFPGA_ARRIA5
51
52config TARGET_SOCFPGA_CYCLONE5_SOCDK
53	bool "Altera SOCFPGA SoCDK (Cyclone V)"
54	select TARGET_SOCFPGA_CYCLONE5
55
56config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
57	bool "Devboards DBM-SoC1 (Cyclone V)"
58	select TARGET_SOCFPGA_CYCLONE5
59
60config TARGET_SOCFPGA_EBV_SOCRATES
61	bool "EBV SoCrates (Cyclone V)"
62	select TARGET_SOCFPGA_CYCLONE5
63
64config TARGET_SOCFPGA_IS1
65	bool "IS1 (Cyclone V)"
66	select TARGET_SOCFPGA_CYCLONE5
67
68config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
69	bool "samtec VIN|ING FPGA (Cyclone V)"
70	select BOARD_LATE_INIT
71	select TARGET_SOCFPGA_CYCLONE5
72
73config TARGET_SOCFPGA_SR1500
74	bool "SR1500 (Cyclone V)"
75	select TARGET_SOCFPGA_CYCLONE5
76
77config TARGET_SOCFPGA_STRATIX10_SOCDK
78	bool "Intel SOCFPGA SoCDK (Stratix 10)"
79	select TARGET_SOCFPGA_STRATIX10
80
81config TARGET_SOCFPGA_TERASIC_DE0_NANO
82	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
83	select TARGET_SOCFPGA_CYCLONE5
84
85config TARGET_SOCFPGA_TERASIC_DE10_NANO
86	bool "Terasic DE10-Nano (Cyclone V)"
87	select TARGET_SOCFPGA_CYCLONE5
88
89config TARGET_SOCFPGA_TERASIC_DE1_SOC
90	bool "Terasic DE1-SoC (Cyclone V)"
91	select TARGET_SOCFPGA_CYCLONE5
92
93config TARGET_SOCFPGA_TERASIC_SOCKIT
94	bool "Terasic SoCkit (Cyclone V)"
95	select TARGET_SOCFPGA_CYCLONE5
96
97endchoice
98
99config SYS_BOARD
100	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
101	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
102	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
103	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
104	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
105	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
106	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
107	default "is1" if TARGET_SOCFPGA_IS1
108	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
109	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
110	default "sr1500" if TARGET_SOCFPGA_SR1500
111	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
112	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
113
114config SYS_VENDOR
115	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
116	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
117	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
118	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
119	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
120	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
121	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
122	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
123	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
124	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
125	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
126
127config SYS_SOC
128	default "socfpga"
129
130config SYS_CONFIG_NAME
131	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
132	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
133	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
134	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
135	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
136	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
137	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
138	default "socfpga_is1" if TARGET_SOCFPGA_IS1
139	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
140	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
141	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
142	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
143	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
144
145endif
146