17865f4b0SMasahiro Yamadaif ARCH_SOCFPGA 27865f4b0SMasahiro Yamada 3f0fb4fa7SDalon Westergreenconfig SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 4f0fb4fa7SDalon Westergreen default 0xa2 5f0fb4fa7SDalon Westergreen 6cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5 7cd9b7317SMarek Vasut bool 8ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 9cd9b7317SMarek Vasut 10d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10 11d89e979cSLey Foon Tan bool 12901af3e9STien Fong Chee select ALTERA_SDRAM 1358008cbaSMichal Simek select SPL_BOARD_INIT if SPL 14*fe88c2feSMarek Vasut select DM_I2C 158145c1c2SMarek Vasut select DM_RESET 168145c1c2SMarek Vasut select SPL_DM_RESET if SPL 17d89e979cSLey Foon Tan 18cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5 19cd9b7317SMarek Vasut bool 20ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 21ed77aeb5SDinh Nguyen 22ed77aeb5SDinh Nguyenconfig TARGET_SOCFPGA_GEN5 23ed77aeb5SDinh Nguyen bool 24707cd012SLey Foon Tan select ALTERA_SDRAM 25cd9b7317SMarek Vasut 26a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10 27a684729aSLey Foon Tan bool 28a684729aSLey Foon Tan select ARMV8_MULTIENTRY 29a684729aSLey Foon Tan select ARMV8_SET_SMPEN 3058008cbaSMichal Simek select ARMV8_SPIN_TABLE 31a684729aSLey Foon Tan 327865f4b0SMasahiro Yamadachoice 337865f4b0SMasahiro Yamada prompt "Altera SOCFPGA board select" 34a26cd049SJoe Hershberger optional 357865f4b0SMasahiro Yamada 36d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10_SOCDK 37d89e979cSLey Foon Tan bool "Altera SOCFPGA SoCDK (Arria 10)" 38d89e979cSLey Foon Tan select TARGET_SOCFPGA_ARRIA10 39d89e979cSLey Foon Tan 40cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5_SOCDK 41cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Arria V)" 42cd9b7317SMarek Vasut select TARGET_SOCFPGA_ARRIA5 437865f4b0SMasahiro Yamada 44cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5_SOCDK 45cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Cyclone V)" 46cd9b7317SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 477865f4b0SMasahiro Yamada 487fb46430SMarek Vasutconfig TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 497fb46430SMarek Vasut bool "Devboards DBM-SoC1 (Cyclone V)" 507fb46430SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 517fb46430SMarek Vasut 52856b30daSMarek Vasutconfig TARGET_SOCFPGA_EBV_SOCRATES 53856b30daSMarek Vasut bool "EBV SoCrates (Cyclone V)" 54856b30daSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 55856b30daSMarek Vasut 5635546f6fSPavel Machekconfig TARGET_SOCFPGA_IS1 5735546f6fSPavel Machek bool "IS1 (Cyclone V)" 5835546f6fSPavel Machek select TARGET_SOCFPGA_CYCLONE5 5935546f6fSPavel Machek 60569a191aSMarek Vasutconfig TARGET_SOCFPGA_SAMTEC_VINING_FPGA 61569a191aSMarek Vasut bool "samtec VIN|ING FPGA (Cyclone V)" 62e5ec4815STom Rini select BOARD_LATE_INIT 63569a191aSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 64569a191aSMarek Vasut 65cf0a8dabSMarek Vasutconfig TARGET_SOCFPGA_SR1500 66cf0a8dabSMarek Vasut bool "SR1500 (Cyclone V)" 67cf0a8dabSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 68cf0a8dabSMarek Vasut 69a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10_SOCDK 70a684729aSLey Foon Tan bool "Intel SOCFPGA SoCDK (Stratix 10)" 71a684729aSLey Foon Tan select TARGET_SOCFPGA_STRATIX10 72a684729aSLey Foon Tan 7355c7a765SDinh Nguyenconfig TARGET_SOCFPGA_TERASIC_DE0_NANO 7455c7a765SDinh Nguyen bool "Terasic DE0-Nano-Atlas (Cyclone V)" 7555c7a765SDinh Nguyen select TARGET_SOCFPGA_CYCLONE5 7655c7a765SDinh Nguyen 776bd041f0SDalon Westergreenconfig TARGET_SOCFPGA_TERASIC_DE10_NANO 786bd041f0SDalon Westergreen bool "Terasic DE10-Nano (Cyclone V)" 796bd041f0SDalon Westergreen select TARGET_SOCFPGA_CYCLONE5 806bd041f0SDalon Westergreen 81e9c847c3SAnatolij Gustschinconfig TARGET_SOCFPGA_TERASIC_DE1_SOC 82e9c847c3SAnatolij Gustschin bool "Terasic DE1-SoC (Cyclone V)" 83e9c847c3SAnatolij Gustschin select TARGET_SOCFPGA_CYCLONE5 84e9c847c3SAnatolij Gustschin 85952caa28SMarek Vasutconfig TARGET_SOCFPGA_TERASIC_SOCKIT 86952caa28SMarek Vasut bool "Terasic SoCkit (Cyclone V)" 87952caa28SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 88952caa28SMarek Vasut 897865f4b0SMasahiro Yamadaendchoice 907865f4b0SMasahiro Yamada 917865f4b0SMasahiro Yamadaconfig SYS_BOARD 92f0892401SMarek Vasut default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 93d89e979cSLey Foon Tan default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 94f0892401SMarek Vasut default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 957fb46430SMarek Vasut default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 9655c7a765SDinh Nguyen default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 97e9c847c3SAnatolij Gustschin default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 986bd041f0SDalon Westergreen default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 9935546f6fSPavel Machek default "is1" if TARGET_SOCFPGA_IS1 100952caa28SMarek Vasut default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 101856b30daSMarek Vasut default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 102ae9996c8SStefan Roese default "sr1500" if TARGET_SOCFPGA_SR1500 103a684729aSLey Foon Tan default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 104569a191aSMarek Vasut default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1057865f4b0SMasahiro Yamada 1067865f4b0SMasahiro Yamadaconfig SYS_VENDOR 107cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 108d89e979cSLey Foon Tan default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 109cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 110a684729aSLey Foon Tan default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK 1117fb46430SMarek Vasut default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 112856b30daSMarek Vasut default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 113569a191aSMarek Vasut default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 11455c7a765SDinh Nguyen default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 115e9c847c3SAnatolij Gustschin default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1166bd041f0SDalon Westergreen default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 117952caa28SMarek Vasut default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 1187865f4b0SMasahiro Yamada 1197865f4b0SMasahiro Yamadaconfig SYS_SOC 1207865f4b0SMasahiro Yamada default "socfpga" 1217865f4b0SMasahiro Yamada 1227865f4b0SMasahiro Yamadaconfig SYS_CONFIG_NAME 1233cbc7b87SDinh Nguyen default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 124d89e979cSLey Foon Tan default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 1253cbc7b87SDinh Nguyen default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 1267fb46430SMarek Vasut default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 12755c7a765SDinh Nguyen default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 128e9c847c3SAnatolij Gustschin default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1296bd041f0SDalon Westergreen default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 13035546f6fSPavel Machek default "socfpga_is1" if TARGET_SOCFPGA_IS1 131952caa28SMarek Vasut default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 132856b30daSMarek Vasut default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 133ae9996c8SStefan Roese default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 134a684729aSLey Foon Tan default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 135569a191aSMarek Vasut default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1367865f4b0SMasahiro Yamada 1377865f4b0SMasahiro Yamadaendif 138