17865f4b0SMasahiro Yamadaif ARCH_SOCFPGA 27865f4b0SMasahiro Yamada 377d2f7f5SSimon Glassconfig SPL_LIBCOMMON_SUPPORT 477d2f7f5SSimon Glass default y 577d2f7f5SSimon Glass 61646eba8SSimon Glassconfig SPL_LIBDISK_SUPPORT 71646eba8SSimon Glass default y 81646eba8SSimon Glass 9cc4288efSSimon Glassconfig SPL_LIBGENERIC_SUPPORT 10cc4288efSSimon Glass default y 11cc4288efSSimon Glass 121fdf7c64SSimon Glassconfig SPL_MMC_SUPPORT 131fdf7c64SSimon Glass default y if DM_MMC 141fdf7c64SSimon Glass 15d6b9bd89SSimon Glassconfig SPL_NAND_SUPPORT 16d6b9bd89SSimon Glass default y if SPL_NAND_DENALI 17d6b9bd89SSimon Glass 18e00f76ceSSimon Glassconfig SPL_SERIAL_SUPPORT 19e00f76ceSSimon Glass default y 20e00f76ceSSimon Glass 21e404ade4SSimon Glassconfig SPL_SPI_FLASH_SUPPORT 22f35ed9edSSimon Glass default y if SPL_SPI_SUPPORT 23f35ed9edSSimon Glass 24f35ed9edSSimon Glassconfig SPL_SPI_SUPPORT 25e404ade4SSimon Glass default y if DM_SPI 26e404ade4SSimon Glass 2702e69a5dSSimon Glassconfig SPL_WATCHDOG_SUPPORT 2802e69a5dSSimon Glass default y 2902e69a5dSSimon Glass 30cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5 31cd9b7317SMarek Vasut bool 32ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 33cd9b7317SMarek Vasut 34cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5 35cd9b7317SMarek Vasut bool 36ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 37ed77aeb5SDinh Nguyen 38ed77aeb5SDinh Nguyenconfig TARGET_SOCFPGA_GEN5 39ed77aeb5SDinh Nguyen bool 40cd9b7317SMarek Vasut 417865f4b0SMasahiro Yamadachoice 427865f4b0SMasahiro Yamada prompt "Altera SOCFPGA board select" 43a26cd049SJoe Hershberger optional 447865f4b0SMasahiro Yamada 45cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5_SOCDK 46cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Arria V)" 47cd9b7317SMarek Vasut select TARGET_SOCFPGA_ARRIA5 487865f4b0SMasahiro Yamada 49cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5_SOCDK 50cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Cyclone V)" 51cd9b7317SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 527865f4b0SMasahiro Yamada 53d88995a8SMarek Vasutconfig TARGET_SOCFPGA_DENX_MCVEVK 54d88995a8SMarek Vasut bool "DENX MCVEVK (Cyclone V)" 55d88995a8SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 56d88995a8SMarek Vasut 57856b30daSMarek Vasutconfig TARGET_SOCFPGA_EBV_SOCRATES 58856b30daSMarek Vasut bool "EBV SoCrates (Cyclone V)" 59856b30daSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 60856b30daSMarek Vasut 6135546f6fSPavel Machekconfig TARGET_SOCFPGA_IS1 6235546f6fSPavel Machek bool "IS1 (Cyclone V)" 6335546f6fSPavel Machek select TARGET_SOCFPGA_CYCLONE5 6435546f6fSPavel Machek 65569a191aSMarek Vasutconfig TARGET_SOCFPGA_SAMTEC_VINING_FPGA 66569a191aSMarek Vasut bool "samtec VIN|ING FPGA (Cyclone V)" 67*e5ec4815STom Rini select BOARD_LATE_INIT 68569a191aSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 69569a191aSMarek Vasut 70cf0a8dabSMarek Vasutconfig TARGET_SOCFPGA_SR1500 71cf0a8dabSMarek Vasut bool "SR1500 (Cyclone V)" 72cf0a8dabSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 73cf0a8dabSMarek Vasut 7455c7a765SDinh Nguyenconfig TARGET_SOCFPGA_TERASIC_DE0_NANO 7555c7a765SDinh Nguyen bool "Terasic DE0-Nano-Atlas (Cyclone V)" 7655c7a765SDinh Nguyen select TARGET_SOCFPGA_CYCLONE5 7755c7a765SDinh Nguyen 78e9c847c3SAnatolij Gustschinconfig TARGET_SOCFPGA_TERASIC_DE1_SOC 79e9c847c3SAnatolij Gustschin bool "Terasic DE1-SoC (Cyclone V)" 80e9c847c3SAnatolij Gustschin select TARGET_SOCFPGA_CYCLONE5 81e9c847c3SAnatolij Gustschin 82952caa28SMarek Vasutconfig TARGET_SOCFPGA_TERASIC_SOCKIT 83952caa28SMarek Vasut bool "Terasic SoCkit (Cyclone V)" 84952caa28SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 85952caa28SMarek Vasut 867865f4b0SMasahiro Yamadaendchoice 877865f4b0SMasahiro Yamada 887865f4b0SMasahiro Yamadaconfig SYS_BOARD 89f0892401SMarek Vasut default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 90f0892401SMarek Vasut default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 9155c7a765SDinh Nguyen default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 92e9c847c3SAnatolij Gustschin default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 9335546f6fSPavel Machek default "is1" if TARGET_SOCFPGA_IS1 94d88995a8SMarek Vasut default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK 95952caa28SMarek Vasut default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 96856b30daSMarek Vasut default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 97ae9996c8SStefan Roese default "sr1500" if TARGET_SOCFPGA_SR1500 98569a191aSMarek Vasut default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 997865f4b0SMasahiro Yamada 1007865f4b0SMasahiro Yamadaconfig SYS_VENDOR 101cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 102cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 103d88995a8SMarek Vasut default "denx" if TARGET_SOCFPGA_DENX_MCVEVK 104856b30daSMarek Vasut default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 105569a191aSMarek Vasut default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 10655c7a765SDinh Nguyen default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 107e9c847c3SAnatolij Gustschin default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 108952caa28SMarek Vasut default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 1097865f4b0SMasahiro Yamada 1107865f4b0SMasahiro Yamadaconfig SYS_SOC 1117865f4b0SMasahiro Yamada default "socfpga" 1127865f4b0SMasahiro Yamada 1137865f4b0SMasahiro Yamadaconfig SYS_CONFIG_NAME 1143cbc7b87SDinh Nguyen default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 1153cbc7b87SDinh Nguyen default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 11655c7a765SDinh Nguyen default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 117e9c847c3SAnatolij Gustschin default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 11835546f6fSPavel Machek default "socfpga_is1" if TARGET_SOCFPGA_IS1 119d88995a8SMarek Vasut default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK 120952caa28SMarek Vasut default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 121856b30daSMarek Vasut default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 122ae9996c8SStefan Roese default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 123569a191aSMarek Vasut default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1247865f4b0SMasahiro Yamada 1257865f4b0SMasahiro Yamadaendif 126