17865f4b0SMasahiro Yamadaif ARCH_SOCFPGA 27865f4b0SMasahiro Yamada 3f0fb4fa7SDalon Westergreenconfig SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 4f0fb4fa7SDalon Westergreen default 0xa2 5f0fb4fa7SDalon Westergreen 6cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5 7cd9b7317SMarek Vasut bool 8ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 9cd9b7317SMarek Vasut 10d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10 11d89e979cSLey Foon Tan bool 12901af3e9STien Fong Chee select ALTERA_SDRAM 1358008cbaSMichal Simek select SPL_BOARD_INIT if SPL 14fe88c2feSMarek Vasut select DM_I2C 158145c1c2SMarek Vasut select DM_RESET 168145c1c2SMarek Vasut select SPL_DM_RESET if SPL 17*d6a61da4SMarek Vasut select REGMAP 18*d6a61da4SMarek Vasut select SPL_REGMAP if SPL 19*d6a61da4SMarek Vasut select SYSCON 20*d6a61da4SMarek Vasut select SPL_SYSCON if SPL 21*d6a61da4SMarek Vasut select ETH_DESIGNWARE_SOCFPGA 22d89e979cSLey Foon Tan 23cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5 24cd9b7317SMarek Vasut bool 25ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 26ed77aeb5SDinh Nguyen 27ed77aeb5SDinh Nguyenconfig TARGET_SOCFPGA_GEN5 28ed77aeb5SDinh Nguyen bool 29707cd012SLey Foon Tan select ALTERA_SDRAM 30cd9b7317SMarek Vasut 31a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10 32a684729aSLey Foon Tan bool 33a684729aSLey Foon Tan select ARMV8_MULTIENTRY 34a684729aSLey Foon Tan select ARMV8_SET_SMPEN 3558008cbaSMichal Simek select ARMV8_SPIN_TABLE 36a684729aSLey Foon Tan 377865f4b0SMasahiro Yamadachoice 387865f4b0SMasahiro Yamada prompt "Altera SOCFPGA board select" 39a26cd049SJoe Hershberger optional 407865f4b0SMasahiro Yamada 41d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10_SOCDK 42d89e979cSLey Foon Tan bool "Altera SOCFPGA SoCDK (Arria 10)" 43d89e979cSLey Foon Tan select TARGET_SOCFPGA_ARRIA10 44d89e979cSLey Foon Tan 45cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5_SOCDK 46cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Arria V)" 47cd9b7317SMarek Vasut select TARGET_SOCFPGA_ARRIA5 487865f4b0SMasahiro Yamada 49cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5_SOCDK 50cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Cyclone V)" 51cd9b7317SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 527865f4b0SMasahiro Yamada 537fb46430SMarek Vasutconfig TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 547fb46430SMarek Vasut bool "Devboards DBM-SoC1 (Cyclone V)" 557fb46430SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 567fb46430SMarek Vasut 57856b30daSMarek Vasutconfig TARGET_SOCFPGA_EBV_SOCRATES 58856b30daSMarek Vasut bool "EBV SoCrates (Cyclone V)" 59856b30daSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 60856b30daSMarek Vasut 6135546f6fSPavel Machekconfig TARGET_SOCFPGA_IS1 6235546f6fSPavel Machek bool "IS1 (Cyclone V)" 6335546f6fSPavel Machek select TARGET_SOCFPGA_CYCLONE5 6435546f6fSPavel Machek 65569a191aSMarek Vasutconfig TARGET_SOCFPGA_SAMTEC_VINING_FPGA 66569a191aSMarek Vasut bool "samtec VIN|ING FPGA (Cyclone V)" 67e5ec4815STom Rini select BOARD_LATE_INIT 68569a191aSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 69569a191aSMarek Vasut 70cf0a8dabSMarek Vasutconfig TARGET_SOCFPGA_SR1500 71cf0a8dabSMarek Vasut bool "SR1500 (Cyclone V)" 72cf0a8dabSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 73cf0a8dabSMarek Vasut 74a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10_SOCDK 75a684729aSLey Foon Tan bool "Intel SOCFPGA SoCDK (Stratix 10)" 76a684729aSLey Foon Tan select TARGET_SOCFPGA_STRATIX10 77a684729aSLey Foon Tan 7855c7a765SDinh Nguyenconfig TARGET_SOCFPGA_TERASIC_DE0_NANO 7955c7a765SDinh Nguyen bool "Terasic DE0-Nano-Atlas (Cyclone V)" 8055c7a765SDinh Nguyen select TARGET_SOCFPGA_CYCLONE5 8155c7a765SDinh Nguyen 826bd041f0SDalon Westergreenconfig TARGET_SOCFPGA_TERASIC_DE10_NANO 836bd041f0SDalon Westergreen bool "Terasic DE10-Nano (Cyclone V)" 846bd041f0SDalon Westergreen select TARGET_SOCFPGA_CYCLONE5 856bd041f0SDalon Westergreen 86e9c847c3SAnatolij Gustschinconfig TARGET_SOCFPGA_TERASIC_DE1_SOC 87e9c847c3SAnatolij Gustschin bool "Terasic DE1-SoC (Cyclone V)" 88e9c847c3SAnatolij Gustschin select TARGET_SOCFPGA_CYCLONE5 89e9c847c3SAnatolij Gustschin 90952caa28SMarek Vasutconfig TARGET_SOCFPGA_TERASIC_SOCKIT 91952caa28SMarek Vasut bool "Terasic SoCkit (Cyclone V)" 92952caa28SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 93952caa28SMarek Vasut 947865f4b0SMasahiro Yamadaendchoice 957865f4b0SMasahiro Yamada 967865f4b0SMasahiro Yamadaconfig SYS_BOARD 97f0892401SMarek Vasut default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 98d89e979cSLey Foon Tan default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 99f0892401SMarek Vasut default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 1007fb46430SMarek Vasut default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 10155c7a765SDinh Nguyen default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 102e9c847c3SAnatolij Gustschin default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1036bd041f0SDalon Westergreen default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 10435546f6fSPavel Machek default "is1" if TARGET_SOCFPGA_IS1 105952caa28SMarek Vasut default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 106856b30daSMarek Vasut default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 107ae9996c8SStefan Roese default "sr1500" if TARGET_SOCFPGA_SR1500 108a684729aSLey Foon Tan default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 109569a191aSMarek Vasut default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1107865f4b0SMasahiro Yamada 1117865f4b0SMasahiro Yamadaconfig SYS_VENDOR 112cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 113d89e979cSLey Foon Tan default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 114cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 115a684729aSLey Foon Tan default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK 1167fb46430SMarek Vasut default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 117856b30daSMarek Vasut default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 118569a191aSMarek Vasut default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 11955c7a765SDinh Nguyen default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 120e9c847c3SAnatolij Gustschin default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1216bd041f0SDalon Westergreen default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 122952caa28SMarek Vasut default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 1237865f4b0SMasahiro Yamada 1247865f4b0SMasahiro Yamadaconfig SYS_SOC 1257865f4b0SMasahiro Yamada default "socfpga" 1267865f4b0SMasahiro Yamada 1277865f4b0SMasahiro Yamadaconfig SYS_CONFIG_NAME 1283cbc7b87SDinh Nguyen default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 129d89e979cSLey Foon Tan default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 1303cbc7b87SDinh Nguyen default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 1317fb46430SMarek Vasut default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 13255c7a765SDinh Nguyen default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 133e9c847c3SAnatolij Gustschin default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1346bd041f0SDalon Westergreen default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 13535546f6fSPavel Machek default "socfpga_is1" if TARGET_SOCFPGA_IS1 136952caa28SMarek Vasut default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 137856b30daSMarek Vasut default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 138ae9996c8SStefan Roese default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 139a684729aSLey Foon Tan default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 140569a191aSMarek Vasut default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1417865f4b0SMasahiro Yamada 1427865f4b0SMasahiro Yamadaendif 143