17865f4b0SMasahiro Yamadaif ARCH_SOCFPGA 27865f4b0SMasahiro Yamada 3f0fb4fa7SDalon Westergreenconfig SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE 4f0fb4fa7SDalon Westergreen default 0xa2 5f0fb4fa7SDalon Westergreen 6cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5 7cd9b7317SMarek Vasut bool 8ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 9cd9b7317SMarek Vasut 10d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10 11d89e979cSLey Foon Tan bool 120680f1b1SLey Foon Tan select SPL_BOARD_INIT if SPL 13901af3e9STien Fong Chee select ALTERA_SDRAM 14d89e979cSLey Foon Tan 15cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5 16cd9b7317SMarek Vasut bool 17ed77aeb5SDinh Nguyen select TARGET_SOCFPGA_GEN5 18ed77aeb5SDinh Nguyen 19ed77aeb5SDinh Nguyenconfig TARGET_SOCFPGA_GEN5 20ed77aeb5SDinh Nguyen bool 21707cd012SLey Foon Tan select ALTERA_SDRAM 22cd9b7317SMarek Vasut 23*a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10 24*a684729aSLey Foon Tan bool 25*a684729aSLey Foon Tan select ARMV8_MULTIENTRY 26*a684729aSLey Foon Tan select ARMV8_SPIN_TABLE 27*a684729aSLey Foon Tan select ARMV8_SET_SMPEN 28*a684729aSLey Foon Tan 297865f4b0SMasahiro Yamadachoice 307865f4b0SMasahiro Yamada prompt "Altera SOCFPGA board select" 31a26cd049SJoe Hershberger optional 327865f4b0SMasahiro Yamada 33d89e979cSLey Foon Tanconfig TARGET_SOCFPGA_ARRIA10_SOCDK 34d89e979cSLey Foon Tan bool "Altera SOCFPGA SoCDK (Arria 10)" 35d89e979cSLey Foon Tan select TARGET_SOCFPGA_ARRIA10 36d89e979cSLey Foon Tan 37cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_ARRIA5_SOCDK 38cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Arria V)" 39cd9b7317SMarek Vasut select TARGET_SOCFPGA_ARRIA5 407865f4b0SMasahiro Yamada 41cd9b7317SMarek Vasutconfig TARGET_SOCFPGA_CYCLONE5_SOCDK 42cd9b7317SMarek Vasut bool "Altera SOCFPGA SoCDK (Cyclone V)" 43cd9b7317SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 447865f4b0SMasahiro Yamada 457fb46430SMarek Vasutconfig TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 467fb46430SMarek Vasut bool "Devboards DBM-SoC1 (Cyclone V)" 477fb46430SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 487fb46430SMarek Vasut 49856b30daSMarek Vasutconfig TARGET_SOCFPGA_EBV_SOCRATES 50856b30daSMarek Vasut bool "EBV SoCrates (Cyclone V)" 51856b30daSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 52856b30daSMarek Vasut 5335546f6fSPavel Machekconfig TARGET_SOCFPGA_IS1 5435546f6fSPavel Machek bool "IS1 (Cyclone V)" 5535546f6fSPavel Machek select TARGET_SOCFPGA_CYCLONE5 5635546f6fSPavel Machek 57569a191aSMarek Vasutconfig TARGET_SOCFPGA_SAMTEC_VINING_FPGA 58569a191aSMarek Vasut bool "samtec VIN|ING FPGA (Cyclone V)" 59e5ec4815STom Rini select BOARD_LATE_INIT 60569a191aSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 61569a191aSMarek Vasut 62cf0a8dabSMarek Vasutconfig TARGET_SOCFPGA_SR1500 63cf0a8dabSMarek Vasut bool "SR1500 (Cyclone V)" 64cf0a8dabSMarek Vasut select TARGET_SOCFPGA_CYCLONE5 65cf0a8dabSMarek Vasut 66*a684729aSLey Foon Tanconfig TARGET_SOCFPGA_STRATIX10_SOCDK 67*a684729aSLey Foon Tan bool "Intel SOCFPGA SoCDK (Stratix 10)" 68*a684729aSLey Foon Tan select TARGET_SOCFPGA_STRATIX10 69*a684729aSLey Foon Tan 7055c7a765SDinh Nguyenconfig TARGET_SOCFPGA_TERASIC_DE0_NANO 7155c7a765SDinh Nguyen bool "Terasic DE0-Nano-Atlas (Cyclone V)" 7255c7a765SDinh Nguyen select TARGET_SOCFPGA_CYCLONE5 7355c7a765SDinh Nguyen 746bd041f0SDalon Westergreenconfig TARGET_SOCFPGA_TERASIC_DE10_NANO 756bd041f0SDalon Westergreen bool "Terasic DE10-Nano (Cyclone V)" 766bd041f0SDalon Westergreen select TARGET_SOCFPGA_CYCLONE5 776bd041f0SDalon Westergreen 78e9c847c3SAnatolij Gustschinconfig TARGET_SOCFPGA_TERASIC_DE1_SOC 79e9c847c3SAnatolij Gustschin bool "Terasic DE1-SoC (Cyclone V)" 80e9c847c3SAnatolij Gustschin select TARGET_SOCFPGA_CYCLONE5 81e9c847c3SAnatolij Gustschin 82952caa28SMarek Vasutconfig TARGET_SOCFPGA_TERASIC_SOCKIT 83952caa28SMarek Vasut bool "Terasic SoCkit (Cyclone V)" 84952caa28SMarek Vasut select TARGET_SOCFPGA_CYCLONE5 85952caa28SMarek Vasut 867865f4b0SMasahiro Yamadaendchoice 877865f4b0SMasahiro Yamada 887865f4b0SMasahiro Yamadaconfig SYS_BOARD 89f0892401SMarek Vasut default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 90d89e979cSLey Foon Tan default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 91f0892401SMarek Vasut default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 927fb46430SMarek Vasut default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 9355c7a765SDinh Nguyen default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 94e9c847c3SAnatolij Gustschin default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 956bd041f0SDalon Westergreen default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 9635546f6fSPavel Machek default "is1" if TARGET_SOCFPGA_IS1 97952caa28SMarek Vasut default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 98856b30daSMarek Vasut default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES 99ae9996c8SStefan Roese default "sr1500" if TARGET_SOCFPGA_SR1500 100*a684729aSLey Foon Tan default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 101569a191aSMarek Vasut default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1027865f4b0SMasahiro Yamada 1037865f4b0SMasahiro Yamadaconfig SYS_VENDOR 104cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK 105d89e979cSLey Foon Tan default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK 106cd9b7317SMarek Vasut default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK 107*a684729aSLey Foon Tan default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK 1087fb46430SMarek Vasut default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 109856b30daSMarek Vasut default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES 110569a191aSMarek Vasut default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 11155c7a765SDinh Nguyen default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO 112e9c847c3SAnatolij Gustschin default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1136bd041f0SDalon Westergreen default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO 114952caa28SMarek Vasut default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT 1157865f4b0SMasahiro Yamada 1167865f4b0SMasahiro Yamadaconfig SYS_SOC 1177865f4b0SMasahiro Yamada default "socfpga" 1187865f4b0SMasahiro Yamada 1197865f4b0SMasahiro Yamadaconfig SYS_CONFIG_NAME 1203cbc7b87SDinh Nguyen default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK 121d89e979cSLey Foon Tan default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK 1223cbc7b87SDinh Nguyen default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK 1237fb46430SMarek Vasut default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 12455c7a765SDinh Nguyen default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO 125e9c847c3SAnatolij Gustschin default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC 1266bd041f0SDalon Westergreen default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO 12735546f6fSPavel Machek default "socfpga_is1" if TARGET_SOCFPGA_IS1 128952caa28SMarek Vasut default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT 129856b30daSMarek Vasut default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES 130ae9996c8SStefan Roese default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 131*a684729aSLey Foon Tan default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK 132569a191aSMarek Vasut default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA 1337865f4b0SMasahiro Yamada 1347865f4b0SMasahiro Yamadaendif 135