1 /*
2  * Qualcomm APQ8916 sysmap
3  *
4  * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 #ifndef _MACH_SYSMAP_APQ8016_H
9 #define _MACH_SYSMAP_APQ8016_H
10 
11 #define GICD_BASE			(0x0b000000)
12 #define GICC_BASE			(0x0a20c000)
13 
14 /* Clocks: (from CLK_CTL_BASE)  */
15 #define GPLL0_STATUS			(0x2101C)
16 #define APCS_GPLL_ENA_VOTE		(0x45000)
17 
18 #define SDCC_BCR(n)			((n * 0x1000) + 0x41000)
19 #define SDCC_CMD_RCGR(n)		((n * 0x1000) + 0x41004)
20 #define SDCC_CFG_RCGR(n)		((n * 0x1000) + 0x41008)
21 #define SDCC_M(n)			((n * 0x1000) + 0x4100C)
22 #define SDCC_N(n)			((n * 0x1000) + 0x41010)
23 #define SDCC_D(n)			((n * 0x1000) + 0x41014)
24 #define SDCC_APPS_CBCR(n)		((n * 0x1000) + 0x41018)
25 #define SDCC_AHB_CBCR(n)		((n * 0x1000) + 0x4101C)
26 
27 /* BLSP1 AHB clock (root clock for BLSP) */
28 #define BLSP1_AHB_CBCR			0x1008
29 
30 /* Uart clock control registers */
31 #define BLSP1_UART2_BCR			(0x3028)
32 #define BLSP1_UART2_APPS_CBCR		(0x302C)
33 #define BLSP1_UART2_APPS_CMD_RCGR	(0x3034)
34 #define BLSP1_UART2_APPS_CFG_RCGR	(0x3038)
35 #define BLSP1_UART2_APPS_M		(0x303C)
36 #define BLSP1_UART2_APPS_N		(0x3040)
37 #define BLSP1_UART2_APPS_D		(0x3044)
38 
39 #endif
40