108592136SMateusz Kulikowski /* 208592136SMateusz Kulikowski * Qualcomm APQ8916 sysmap 308592136SMateusz Kulikowski * 408592136SMateusz Kulikowski * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 508592136SMateusz Kulikowski * 608592136SMateusz Kulikowski * SPDX-License-Identifier: GPL-2.0+ 708592136SMateusz Kulikowski */ 808592136SMateusz Kulikowski #ifndef _MACH_SYSMAP_APQ8016_H 908592136SMateusz Kulikowski #define _MACH_SYSMAP_APQ8016_H 1008592136SMateusz Kulikowski 11*7c75f7f1SJorge Ramirez-Ortiz #define GICD_BASE (0x0b000000) 12*7c75f7f1SJorge Ramirez-Ortiz #define GICC_BASE (0x0a20c000) 13*7c75f7f1SJorge Ramirez-Ortiz 14*7c75f7f1SJorge Ramirez-Ortiz /* Clocks: (from CLK_CTL_BASE) */ 15*7c75f7f1SJorge Ramirez-Ortiz #define GPLL0_STATUS (0x2101C) 16*7c75f7f1SJorge Ramirez-Ortiz #define APCS_GPLL_ENA_VOTE (0x45000) 17*7c75f7f1SJorge Ramirez-Ortiz 18*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) 19*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) 20*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) 21*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_M(n) ((n * 0x1000) + 0x4100C) 22*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_N(n) ((n * 0x1000) + 0x41010) 23*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_D(n) ((n * 0x1000) + 0x41014) 24*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) 25*7c75f7f1SJorge Ramirez-Ortiz #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) 26*7c75f7f1SJorge Ramirez-Ortiz 27*7c75f7f1SJorge Ramirez-Ortiz /* BLSP1 AHB clock (root clock for BLSP) */ 28*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_AHB_CBCR 0x1008 29*7c75f7f1SJorge Ramirez-Ortiz 30*7c75f7f1SJorge Ramirez-Ortiz /* Uart clock control registers */ 31*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_BCR (0x3028) 32*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_CBCR (0x302C) 33*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) 34*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_CFG_RCGR (0x3038) 35*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_M (0x303C) 36*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_N (0x3040) 37*7c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_D (0x3044) 3808592136SMateusz Kulikowski 3908592136SMateusz Kulikowski #endif 40