183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 208592136SMateusz Kulikowski /* 308592136SMateusz Kulikowski * Qualcomm APQ8916 sysmap 408592136SMateusz Kulikowski * 508592136SMateusz Kulikowski * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 608592136SMateusz Kulikowski */ 708592136SMateusz Kulikowski #ifndef _MACH_SYSMAP_APQ8016_H 808592136SMateusz Kulikowski #define _MACH_SYSMAP_APQ8016_H 908592136SMateusz Kulikowski 107c75f7f1SJorge Ramirez-Ortiz #define GICD_BASE (0x0b000000) 117c75f7f1SJorge Ramirez-Ortiz #define GICC_BASE (0x0a20c000) 127c75f7f1SJorge Ramirez-Ortiz 137c75f7f1SJorge Ramirez-Ortiz /* Clocks: (from CLK_CTL_BASE) */ 147c75f7f1SJorge Ramirez-Ortiz #define GPLL0_STATUS (0x2101C) 157c75f7f1SJorge Ramirez-Ortiz #define APCS_GPLL_ENA_VOTE (0x45000) 16*640dc349SRamon Fried #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004) 177c75f7f1SJorge Ramirez-Ortiz 187c75f7f1SJorge Ramirez-Ortiz #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) 197c75f7f1SJorge Ramirez-Ortiz #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) 207c75f7f1SJorge Ramirez-Ortiz #define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) 217c75f7f1SJorge Ramirez-Ortiz #define SDCC_M(n) ((n * 0x1000) + 0x4100C) 227c75f7f1SJorge Ramirez-Ortiz #define SDCC_N(n) ((n * 0x1000) + 0x41010) 237c75f7f1SJorge Ramirez-Ortiz #define SDCC_D(n) ((n * 0x1000) + 0x41014) 247c75f7f1SJorge Ramirez-Ortiz #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) 257c75f7f1SJorge Ramirez-Ortiz #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) 267c75f7f1SJorge Ramirez-Ortiz 277c75f7f1SJorge Ramirez-Ortiz /* BLSP1 AHB clock (root clock for BLSP) */ 287c75f7f1SJorge Ramirez-Ortiz #define BLSP1_AHB_CBCR 0x1008 297c75f7f1SJorge Ramirez-Ortiz 307c75f7f1SJorge Ramirez-Ortiz /* Uart clock control registers */ 317c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_BCR (0x3028) 327c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_CBCR (0x302C) 337c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_CMD_RCGR (0x3034) 347c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_CFG_RCGR (0x3038) 357c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_M (0x303C) 367c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_N (0x3040) 377c75f7f1SJorge Ramirez-Ortiz #define BLSP1_UART2_APPS_D (0x3044) 3808592136SMateusz Kulikowski 3908592136SMateusz Kulikowski #endif 40