1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Qualcomm APQ8016, APQ8096 4 * 5 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> 6 */ 7 #ifndef _CLOCK_SNAPDRAGON_H 8 #define _CLOCK_SNAPDRAGON_H 9 10 #define CFG_CLK_SRC_CXO (0 << 8) 11 #define CFG_CLK_SRC_GPLL0 (1 << 8) 12 #define CFG_CLK_SRC_MASK (7 << 8) 13 14 struct pll_vote_clk { 15 uintptr_t status; 16 int status_bit; 17 uintptr_t ena_vote; 18 int vote_bit; 19 }; 20 21 struct vote_clk { 22 uintptr_t cbcr_reg; 23 uintptr_t ena_vote; 24 int vote_bit; 25 }; 26 struct bcr_regs { 27 uintptr_t cfg_rcgr; 28 uintptr_t cmd_rcgr; 29 uintptr_t M; 30 uintptr_t N; 31 uintptr_t D; 32 }; 33 34 struct msm_clk_priv { 35 phys_addr_t base; 36 }; 37 38 void clk_enable_gpll0(phys_addr_t base, const struct pll_vote_clk *gpll0); 39 void clk_bcr_update(phys_addr_t apps_cmd_rgcr); 40 void clk_enable_cbc(phys_addr_t cbcr); 41 void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); 42 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, 43 int div, int m, int n, int source); 44 45 #endif 46