1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Qualcomm APQ8016, APQ8096
4  *
5  * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
6  */
7 #ifndef _CLOCK_SNAPDRAGON_H
8 #define _CLOCK_SNAPDRAGON_H
9 
10 #define CFG_CLK_SRC_CXO   (0 << 8)
11 #define CFG_CLK_SRC_GPLL0 (1 << 8)
12 #define CFG_CLK_SRC_MASK  (7 << 8)
13 
14 struct gpll0_ctrl {
15 	uintptr_t status;
16 	int status_bit;
17 	uintptr_t ena_vote;
18 	int vote_bit;
19 };
20 
21 struct bcr_regs {
22 	uintptr_t cfg_rcgr;
23 	uintptr_t cmd_rcgr;
24 	uintptr_t M;
25 	uintptr_t N;
26 	uintptr_t D;
27 };
28 
29 struct msm_clk_priv {
30 	phys_addr_t base;
31 };
32 
33 void clk_enable_gpll0(phys_addr_t base, const struct gpll0_ctrl *pll0);
34 void clk_bcr_update(phys_addr_t apps_cmd_rgcr);
35 void clk_enable_cbc(phys_addr_t cbcr);
36 void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
37 			  int div, int m, int n, int source);
38 
39 #endif
40