1 /*
2  * Clock drivers for Qualcomm APQ8096
3  *
4  * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
5  *
6  * Based on Little Kernel driver, simplified
7  *
8  * SPDX-License-Identifier:	BSD-3-Clause
9  */
10 
11 #include <common.h>
12 #include <clk-uclass.h>
13 #include <dm.h>
14 #include <errno.h>
15 #include <asm/io.h>
16 #include <linux/bitops.h>
17 #include "clock-snapdragon.h"
18 
19 /* GPLL0 clock control registers */
20 #define GPLL0_STATUS_ACTIVE		BIT(30)
21 #define APCS_GPLL_ENA_VOTE_GPLL0	BIT(0)
22 
23 static const struct bcr_regs sdc_regs = {
24 	.cfg_rcgr = SDCC2_CFG_RCGR,
25 	.cmd_rcgr = SDCC2_CMD_RCGR,
26 	.M = SDCC2_M,
27 	.N = SDCC2_N,
28 	.D = SDCC2_D,
29 };
30 
31 static const struct gpll0_ctrl gpll0_ctrl = {
32 	.status = GPLL0_STATUS,
33 	.status_bit = GPLL0_STATUS_ACTIVE,
34 	.ena_vote = APCS_GPLL_ENA_VOTE,
35 	.vote_bit = APCS_GPLL_ENA_VOTE_GPLL0,
36 };
37 
38 static int clk_init_sdc(struct msm_clk_priv *priv, uint rate)
39 {
40 	int div = 3;
41 
42 	clk_enable_cbc(priv->base + SDCC2_AHB_CBCR);
43 	clk_rcg_set_rate_mnd(priv->base, &sdc_regs, div, 0, 0,
44 			     CFG_CLK_SRC_GPLL0);
45 	clk_enable_gpll0(priv->base, &gpll0_ctrl);
46 	clk_enable_cbc(priv->base + SDCC2_APPS_CBCR);
47 
48 	return rate;
49 }
50 
51 ulong msm_set_rate(struct clk *clk, ulong rate)
52 {
53 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
54 
55 	switch (clk->id) {
56 	case 0: /* SDC1 */
57 		return clk_init_sdc(priv, rate);
58 		break;
59 	default:
60 		return 0;
61 	}
62 }
63