1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2225f5eecSMinkyu Kang /* 3225f5eecSMinkyu Kang * Copyright (C) 2011 Samsung Electronics 4225f5eecSMinkyu Kang * Heungjun Kim <riverful.kim@samsung.com> 5225f5eecSMinkyu Kang * Minkyu Kang <mk7.kang@samsung.com> 6225f5eecSMinkyu Kang */ 7225f5eecSMinkyu Kang 8225f5eecSMinkyu Kang #ifndef __ASM_ARM_ARCH_WATCHDOG_H_ 9225f5eecSMinkyu Kang #define __ASM_ARM_ARCH_WATCHDOG_H_ 10225f5eecSMinkyu Kang 11225f5eecSMinkyu Kang #define WTCON_RESET_OFFSET 0 12225f5eecSMinkyu Kang #define WTCON_INTEN_OFFSET 2 13225f5eecSMinkyu Kang #define WTCON_CLKSEL_OFFSET 3 14225f5eecSMinkyu Kang #define WTCON_EN_OFFSET 5 15225f5eecSMinkyu Kang #define WTCON_PRE_OFFSET 8 16225f5eecSMinkyu Kang 17225f5eecSMinkyu Kang #define WTCON_CLK_16 0x0 18225f5eecSMinkyu Kang #define WTCON_CLK_32 0x1 19225f5eecSMinkyu Kang #define WTCON_CLK_64 0x2 20225f5eecSMinkyu Kang #define WTCON_CLK_128 0x3 21225f5eecSMinkyu Kang 22225f5eecSMinkyu Kang #define WTCON_CLK(x) ((x & 0x3) << WTCON_CLKSEL_OFFSET) 23225f5eecSMinkyu Kang #define WTCON_PRESCALER(x) ((x) << WTCON_PRE_OFFSET) 24225f5eecSMinkyu Kang #define WTCON_EN (0x1 << WTCON_EN_OFFSET) 25225f5eecSMinkyu Kang #define WTCON_RESET (0x1 << WTCON_RESET_OFFSET) 26225f5eecSMinkyu Kang #define WTCON_INT (0x1 << WTCON_INTEN_OFFSET) 27225f5eecSMinkyu Kang 28225f5eecSMinkyu Kang #ifndef __ASSEMBLY__ 29225f5eecSMinkyu Kang struct s5p_watchdog { 30225f5eecSMinkyu Kang unsigned int wtcon; 31225f5eecSMinkyu Kang unsigned int wtdat; 32225f5eecSMinkyu Kang unsigned int wtcnt; 33225f5eecSMinkyu Kang unsigned int wtclrint; 34225f5eecSMinkyu Kang }; 35225f5eecSMinkyu Kang 36225f5eecSMinkyu Kang /* functions */ 37225f5eecSMinkyu Kang void wdt_stop(void); 38225f5eecSMinkyu Kang void wdt_start(unsigned int timeout); 39225f5eecSMinkyu Kang #endif /* __ASSEMBLY__ */ 40225f5eecSMinkyu Kang 41225f5eecSMinkyu Kang #endif 42