1 /*
2  * Copyright (c) 2016 Rockchip Electronics Co., Ltd
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <asm/armv8/mmu.h>
9 #include <asm/io.h>
10 #include <asm/arch/hardware.h>
11 
12 DECLARE_GLOBAL_DATA_PTR;
13 
14 #define GRF_EMMCCORE_CON11 0xff77f02c
15 
16 static struct mm_region rk3399_mem_map[] = {
17 	{
18 		.virt = 0x0UL,
19 		.phys = 0x0UL,
20 		.size = 0xf8000000UL,
21 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
22 			 PTE_BLOCK_INNER_SHARE
23 	}, {
24 		.virt = 0xf8000000UL,
25 		.phys = 0xf8000000UL,
26 		.size = 0x08000000UL,
27 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
28 			 PTE_BLOCK_NON_SHARE |
29 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
30 	}, {
31 		/* List terminator */
32 		0,
33 	}
34 };
35 
36 struct mm_region *mem_map = rk3399_mem_map;
37 
38 int dram_init_banksize(void)
39 {
40 	size_t max_size = min((unsigned long)gd->ram_size, gd->ram_top);
41 
42 	/* Reserve 0x200000 for ATF bl31 */
43 	gd->bd->bi_dram[0].start = 0x200000;
44 	gd->bd->bi_dram[0].size = max_size - gd->bd->bi_dram[0].start;
45 
46 	return 0;
47 }
48 
49 int arch_cpu_init(void)
50 {
51 	/* We do some SoC one time setting here. */
52 
53 	/* Emmc clock generator: disable the clock multipilier */
54 	rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff);
55 
56 	return 0;
57 }
58