1 /* 2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <debug_uart.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <led.h> 12 #include <malloc.h> 13 #include <ram.h> 14 #include <spl.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/periph.h> 20 #include <asm/arch/sdram.h> 21 #include <asm/arch/timer.h> 22 #include <dm/pinctrl.h> 23 #include <dm/root.h> 24 #include <dm/test.h> 25 #include <dm/util.h> 26 #include <power/regulator.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 u32 spl_boot_device(void) 31 { 32 return BOOT_DEVICE_MMC1; 33 } 34 35 u32 spl_boot_mode(const u32 boot_device) 36 { 37 return MMCSD_MODE_RAW; 38 } 39 40 #define TIMER_CHN10_BASE 0xff8680a0 41 #define TIMER_END_COUNT_L 0x00 42 #define TIMER_END_COUNT_H 0x04 43 #define TIMER_INIT_COUNT_L 0x10 44 #define TIMER_INIT_COUNT_H 0x14 45 #define TIMER_CONTROL_REG 0x1c 46 47 #define TIMER_EN 0x1 48 #define TIMER_FMODE (0 << 1) 49 #define TIMER_RMODE (1 << 1) 50 51 void secure_timer_init(void) 52 { 53 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); 54 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); 55 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); 56 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); 57 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); 58 } 59 60 #define GRF_EMMCCORE_CON11 0xff77f02c 61 void board_init_f(ulong dummy) 62 { 63 struct udevice *pinctrl; 64 struct udevice *dev; 65 int ret; 66 67 /* Example code showing how to enable the debug UART on RK3288 */ 68 #include <asm/arch/grf_rk3399.h> 69 /* Enable early UART2 channel C on the RK3399 */ 70 #define GRF_BASE 0xff770000 71 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; 72 73 rk_clrsetreg(&grf->gpio4c_iomux, 74 GRF_GPIO4C3_SEL_MASK, 75 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); 76 rk_clrsetreg(&grf->gpio4c_iomux, 77 GRF_GPIO4C4_SEL_MASK, 78 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); 79 /* Set channel C as UART2 input */ 80 rk_clrsetreg(&grf->soc_con7, 81 GRF_UART_DBG_SEL_MASK, 82 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); 83 #define EARLY_UART 84 #ifdef EARLY_UART 85 /* 86 * Debug UART can be used from here if required: 87 * 88 * debug_uart_init(); 89 * printch('a'); 90 * printhex8(0x1234); 91 * printascii("string"); 92 */ 93 debug_uart_init(); 94 printascii("U-Boot SPL board init"); 95 #endif 96 /* Emmc clock generator: disable the clock multipilier */ 97 rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); 98 99 ret = spl_init(); 100 if (ret) { 101 debug("spl_init() failed: %d\n", ret); 102 hang(); 103 } 104 105 secure_timer_init(); 106 107 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 108 if (ret) { 109 debug("Pinctrl init failed: %d\n", ret); 110 return; 111 } 112 113 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 114 if (ret) { 115 debug("DRAM init failed: %d\n", ret); 116 return; 117 } 118 } 119 120 void spl_board_init(void) 121 { 122 struct udevice *pinctrl; 123 int ret; 124 125 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 126 if (ret) { 127 debug("%s: Cannot find pinctrl device\n", __func__); 128 goto err; 129 } 130 131 /* Enable debug UART */ 132 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); 133 if (ret) { 134 debug("%s: Failed to set up console UART\n", __func__); 135 goto err; 136 } 137 138 preloader_console_init(); 139 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 140 back_to_bootrom(); 141 #endif 142 return; 143 err: 144 printf("spl_board_init: Error %d\n", ret); 145 146 /* No way to report error here */ 147 hang(); 148 } 149 150 #ifdef CONFIG_SPL_LOAD_FIT 151 int board_fit_config_name_match(const char *name) 152 { 153 /* Just empty function now - can't decide what to choose */ 154 debug("%s: %s\n", __func__, name); 155 156 return 0; 157 } 158 #endif 159