1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH 5 */ 6 7 #include <common.h> 8 #include <debug_uart.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <spl.h> 12 #include <spl_gpio.h> 13 #include <syscon.h> 14 #include <asm/io.h> 15 #include <asm/arch/bootrom.h> 16 #include <asm/arch/clock.h> 17 #include <asm/arch/grf_rk3399.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/periph.h> 20 #include <asm/arch/sys_proto.h> 21 #include <dm/pinctrl.h> 22 23 void board_return_to_bootrom(void) 24 { 25 back_to_bootrom(BROM_BOOT_NEXTSTAGE); 26 } 27 28 static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { 29 [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", 30 [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", 31 [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", 32 }; 33 34 const char *board_spl_was_booted_from(void) 35 { 36 u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR); 37 const char *bootdevice_ofpath = NULL; 38 39 if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) 40 bootdevice_ofpath = boot_devices[bootdevice_brom_id]; 41 42 if (bootdevice_ofpath) 43 debug("%s: brom_bootdevice_id %x maps to '%s'\n", 44 __func__, bootdevice_brom_id, bootdevice_ofpath); 45 else 46 debug("%s: failed to resolve brom_bootdevice_id %x\n", 47 __func__, bootdevice_brom_id); 48 49 return bootdevice_ofpath; 50 } 51 52 u32 spl_boot_device(void) 53 { 54 u32 boot_device = BOOT_DEVICE_MMC1; 55 56 if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) 57 return BOOT_DEVICE_BOOTROM; 58 59 return boot_device; 60 } 61 62 const char *spl_decode_boot_device(u32 boot_device) 63 { 64 int i; 65 static const struct { 66 u32 boot_device; 67 const char *ofpath; 68 } spl_boot_devices_tbl[] = { 69 { BOOT_DEVICE_MMC1, "/dwmmc@fe320000" }, 70 { BOOT_DEVICE_MMC2, "/sdhci@fe330000" }, 71 { BOOT_DEVICE_SPI, "/spi@ff1d0000" }, 72 }; 73 74 for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i) 75 if (spl_boot_devices_tbl[i].boot_device == boot_device) 76 return spl_boot_devices_tbl[i].ofpath; 77 78 return NULL; 79 } 80 81 void spl_perform_fixups(struct spl_image_info *spl_image) 82 { 83 void *blob = spl_image->fdt_addr; 84 const char *boot_ofpath; 85 int chosen; 86 87 /* 88 * Inject the ofpath of the device the full U-Boot (or Linux in 89 * Falcon-mode) was booted from into the FDT, if a FDT has been 90 * loaded at the same time. 91 */ 92 if (!blob) 93 return; 94 95 boot_ofpath = spl_decode_boot_device(spl_image->boot_device); 96 if (!boot_ofpath) { 97 pr_err("%s: could not map boot_device to ofpath\n", __func__); 98 return; 99 } 100 101 chosen = fdt_find_or_add_subnode(blob, 0, "chosen"); 102 if (chosen < 0) { 103 pr_err("%s: could not find/create '/chosen'\n", __func__); 104 return; 105 } 106 fdt_setprop_string(blob, chosen, 107 "u-boot,spl-boot-device", boot_ofpath); 108 } 109 110 #define TIMER_CHN10_BASE 0xff8680a0 111 #define TIMER_END_COUNT_L 0x00 112 #define TIMER_END_COUNT_H 0x04 113 #define TIMER_INIT_COUNT_L 0x10 114 #define TIMER_INIT_COUNT_H 0x14 115 #define TIMER_CONTROL_REG 0x1c 116 117 #define TIMER_EN 0x1 118 #define TIMER_FMODE (0 << 1) 119 #define TIMER_RMODE (1 << 1) 120 121 void secure_timer_init(void) 122 { 123 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L); 124 writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H); 125 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L); 126 writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H); 127 writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG); 128 } 129 130 void board_debug_uart_init(void) 131 { 132 #define GRF_BASE 0xff770000 133 #define GPIO0_BASE 0xff720000 134 #define PMUGRF_BASE 0xff320000 135 struct rk3399_grf_regs * const grf = (void *)GRF_BASE; 136 #ifdef CONFIG_TARGET_CHROMEBOOK_BOB 137 struct rk3399_pmugrf_regs * const pmugrf = (void *)PMUGRF_BASE; 138 struct rockchip_gpio_regs * const gpio = (void *)GPIO0_BASE; 139 #endif 140 141 #if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) 142 /* Enable early UART0 on the RK3399 */ 143 rk_clrsetreg(&grf->gpio2c_iomux, 144 GRF_GPIO2C0_SEL_MASK, 145 GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT); 146 rk_clrsetreg(&grf->gpio2c_iomux, 147 GRF_GPIO2C1_SEL_MASK, 148 GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT); 149 #else 150 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB 151 rk_setreg(&grf->io_vsel, 1 << 0); 152 153 /* 154 * Let's enable these power rails here, we are already running the SPI 155 * Flash based code. 156 */ 157 spl_gpio_output(gpio, GPIO(BANK_B, 2), 1); /* PP1500_EN */ 158 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 2), GPIO_PULL_NORMAL); 159 160 spl_gpio_output(gpio, GPIO(BANK_B, 4), 1); /* PP3000_EN */ 161 spl_gpio_set_pull(&pmugrf->gpio0_p, GPIO(BANK_B, 4), GPIO_PULL_NORMAL); 162 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ 163 164 /* Enable early UART2 channel C on the RK3399 */ 165 rk_clrsetreg(&grf->gpio4c_iomux, 166 GRF_GPIO4C3_SEL_MASK, 167 GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT); 168 rk_clrsetreg(&grf->gpio4c_iomux, 169 GRF_GPIO4C4_SEL_MASK, 170 GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT); 171 /* Set channel C as UART2 input */ 172 rk_clrsetreg(&grf->soc_con7, 173 GRF_UART_DBG_SEL_MASK, 174 GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT); 175 #endif 176 } 177 178 void board_init_f(ulong dummy) 179 { 180 struct udevice *pinctrl; 181 struct udevice *dev; 182 struct rk3399_pmusgrf_regs *sgrf; 183 struct rk3399_grf_regs *grf; 184 int ret; 185 186 #define EARLY_UART 187 #ifdef EARLY_UART 188 debug_uart_init(); 189 190 # ifdef CONFIG_TARGET_CHROMEBOOK_BOB 191 int sum, i; 192 193 /* 194 * Add a delay and ensure that the compiler does not optimise this out. 195 * This is needed since the power rails tail a while to turn on, and 196 * we get garbage serial output otherwise. 197 */ 198 sum = 0; 199 for (i = 0; i < 150000; i++) 200 sum += i; 201 gru_dummy_function(sum); 202 #endif /* CONFIG_TARGET_CHROMEBOOK_BOB */ 203 204 /* 205 * Debug UART can be used from here if required: 206 * 207 * debug_uart_init(); 208 * printch('a'); 209 * printhex8(0x1234); 210 * printascii("string"); 211 */ 212 printascii("U-Boot SPL board init\n"); 213 #endif 214 215 ret = spl_early_init(); 216 if (ret) { 217 debug("spl_early_init() failed: %d\n", ret); 218 hang(); 219 } 220 221 /* 222 * Disable DDR and SRAM security regions. 223 * 224 * As we are entered from the BootROM, the region from 225 * 0x0 through 0xfffff (i.e. the first MB of memory) will 226 * be protected. This will cause issues with the DW_MMC 227 * driver, which tries to DMA from/to the stack (likely) 228 * located in this range. 229 */ 230 sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); 231 rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0); 232 rk_clrreg(&sgrf->slv_secure_con4, 0x2000); 233 234 /* eMMC clock generator: disable the clock multipilier */ 235 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 236 rk_clrreg(&grf->emmccore_con[11], 0x0ff); 237 238 secure_timer_init(); 239 240 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 241 if (ret) { 242 pr_err("Pinctrl init failed: %d\n", ret); 243 return; 244 } 245 246 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 247 if (ret) { 248 pr_err("DRAM init failed: %d\n", ret); 249 return; 250 } 251 } 252 253 #ifdef CONFIG_SPL_LOAD_FIT 254 int board_fit_config_name_match(const char *name) 255 { 256 /* Just empty function now - can't decide what to choose */ 257 debug("%s: %s\n", __func__, name); 258 259 return 0; 260 } 261 #endif 262