1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co., Ltd 3 * Copyright (c) 2016 Andreas Färber 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/armv8/mmu.h> 10 #include <asm/io.h> 11 #include <asm/arch/clock.h> 12 #include <asm/arch/cru_rk3368.h> 13 #include <asm/arch/grf_rk3368.h> 14 #include <syscon.h> 15 16 #define IMEM_BASE 0xFF8C0000 17 18 /* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */ 19 #define MCU_SRAM_BASE (IMEM_BASE + 1024 * 4) 20 #define MCU_SRAM_BASE_BIT31_BIT28 ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28) 21 #define MCU_SRAM_BASE_BIT27_BIT12 ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12) 22 /* exsram may using by mcu to accessing dram(0x0-0x20000000) */ 23 #define MCU_EXSRAM_BASE (0) 24 #define MCU_EXSRAM_BASE_BIT31_BIT28 ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28) 25 #define MCU_EXSRAM_BASE_BIT27_BIT12 ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12) 26 /* experi no used, reserved value = 0 */ 27 #define MCU_EXPERI_BASE (0) 28 #define MCU_EXPERI_BASE_BIT31_BIT28 ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28) 29 #define MCU_EXPERI_BASE_BIT27_BIT12 ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12) 30 31 static struct mm_region rk3368_mem_map[] = { 32 { 33 .virt = 0x0UL, 34 .phys = 0x0UL, 35 .size = 0x80000000UL, 36 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 37 PTE_BLOCK_INNER_SHARE 38 }, { 39 .virt = 0xf0000000UL, 40 .phys = 0xf0000000UL, 41 .size = 0x10000000UL, 42 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 43 PTE_BLOCK_NON_SHARE | 44 PTE_BLOCK_PXN | PTE_BLOCK_UXN 45 }, { 46 /* List terminator */ 47 0, 48 } 49 }; 50 51 struct mm_region *mem_map = rk3368_mem_map; 52 53 #ifdef CONFIG_ARCH_EARLY_INIT_R 54 static int mcu_init(void) 55 { 56 struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 57 struct rk3368_cru *cru = rockchip_get_cru(); 58 59 rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK, 60 MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT); 61 rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK, 62 MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT); 63 rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK, 64 MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT); 65 rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK, 66 MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT); 67 rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK, 68 MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT); 69 rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK, 70 MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT); 71 72 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, 73 (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) | 74 (5 << MCU_CLK_DIV_SHIFT)); 75 76 /* mcu dereset, for start running */ 77 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); 78 79 return 0; 80 } 81 82 int arch_early_init_r(void) 83 { 84 return mcu_init(); 85 } 86 #endif 87