1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/periph.h> 15 #include <asm/arch/pmu_rk3288.h> 16 #include <asm/arch/qos_rk3288.h> 17 #include <asm/arch/boot_mode.h> 18 #include <asm/gpio.h> 19 #include <dm/pinctrl.h> 20 #include <dt-bindings/clock/rk3288-cru.h> 21 #include <power/regulator.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define PMU_BASE 0xff730000 26 27 static void setup_boot_mode(void) 28 { 29 struct rk3288_pmu *const pmu = (void *)PMU_BASE; 30 int boot_mode = readl(&pmu->sys_reg[0]); 31 32 debug("boot mode %x.\n", boot_mode); 33 34 /* Clear boot mode */ 35 writel(BOOT_NORMAL, &pmu->sys_reg[0]); 36 37 switch (boot_mode) { 38 case BOOT_FASTBOOT: 39 printf("enter fastboot!\n"); 40 env_set("preboot", "setenv preboot; fastboot usb0"); 41 break; 42 case BOOT_UMS: 43 printf("enter UMS!\n"); 44 env_set("preboot", "setenv preboot; if mmc dev 0;" 45 "then ums mmc 0; else ums mmc 1;fi"); 46 break; 47 } 48 } 49 50 __weak int rk_board_late_init(void) 51 { 52 return 0; 53 } 54 55 int rk3288_qos_init(void) 56 { 57 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; 58 /* set vop qos to higher priority */ 59 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); 60 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); 61 62 if (!fdt_node_check_compatible(gd->fdt_blob, 0, 63 "rockchip,rk3288-tinker")) 64 { 65 /* set isp qos to higher priority */ 66 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); 67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); 68 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); 69 } 70 return 0; 71 } 72 73 int board_late_init(void) 74 { 75 setup_boot_mode(); 76 rk3288_qos_init(); 77 78 return rk_board_late_init(); 79 } 80 81 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 82 static int veyron_init(void) 83 { 84 struct udevice *dev; 85 struct clk clk; 86 int ret; 87 88 ret = regulator_get_by_platname("vdd_arm", &dev); 89 if (ret) { 90 debug("Cannot set regulator name\n"); 91 return ret; 92 } 93 94 /* Slowly raise to max CPU voltage to prevent overshoot */ 95 ret = regulator_set_value(dev, 1200000); 96 if (ret) 97 return ret; 98 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ 99 ret = regulator_set_value(dev, 1400000); 100 if (ret) 101 return ret; 102 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ 103 104 ret = rockchip_get_clk(&clk.dev); 105 if (ret) 106 return ret; 107 clk.id = PLL_APLL; 108 ret = clk_set_rate(&clk, 1800000000); 109 if (IS_ERR_VALUE(ret)) 110 return ret; 111 112 return 0; 113 } 114 #endif 115 116 int board_init(void) 117 { 118 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 119 struct udevice *pinctrl; 120 int ret; 121 122 /* 123 * We need to implement sdcard iomux here for the further 124 * initlization, otherwise, it'll hit sdcard command sending 125 * timeout exception. 126 */ 127 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 128 if (ret) { 129 debug("%s: Cannot find pinctrl device\n", __func__); 130 goto err; 131 } 132 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); 133 if (ret) { 134 debug("%s: Failed to set up SD card\n", __func__); 135 goto err; 136 } 137 138 return 0; 139 err: 140 printf("board_init: Error %d\n", ret); 141 142 /* No way to report error here */ 143 hang(); 144 145 return -1; 146 #else 147 int ret; 148 149 /* We do some SoC one time setting here */ 150 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { 151 ret = veyron_init(); 152 if (ret) 153 return ret; 154 } 155 156 return 0; 157 #endif 158 } 159 160 #ifndef CONFIG_SYS_DCACHE_OFF 161 void enable_caches(void) 162 { 163 /* Enable D-cache. I-cache is already enabled in start.S */ 164 dcache_enable(); 165 } 166 #endif 167 168 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 169 #include <usb.h> 170 #include <usb/dwc2_udc.h> 171 172 static struct dwc2_plat_otg_data rk3288_otg_data = { 173 .rx_fifo_sz = 512, 174 .np_tx_fifo_sz = 16, 175 .tx_fifo_sz = 128, 176 }; 177 178 int board_usb_init(int index, enum usb_init_type init) 179 { 180 int node, phy_node; 181 const char *mode; 182 bool matched = false; 183 const void *blob = gd->fdt_blob; 184 u32 grf_phy_offset; 185 186 /* find the usb_otg node */ 187 node = fdt_node_offset_by_compatible(blob, -1, 188 "rockchip,rk3288-usb"); 189 190 while (node > 0) { 191 mode = fdt_getprop(blob, node, "dr_mode", NULL); 192 if (mode && strcmp(mode, "otg") == 0) { 193 matched = true; 194 break; 195 } 196 197 node = fdt_node_offset_by_compatible(blob, node, 198 "rockchip,rk3288-usb"); 199 } 200 if (!matched) { 201 debug("Not found usb_otg device\n"); 202 return -ENODEV; 203 } 204 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); 205 206 node = fdtdec_lookup_phandle(blob, node, "phys"); 207 if (node <= 0) { 208 debug("Not found usb phy device\n"); 209 return -ENODEV; 210 } 211 212 phy_node = fdt_parent_offset(blob, node); 213 if (phy_node <= 0) { 214 debug("Not found usb phy device\n"); 215 return -ENODEV; 216 } 217 218 rk3288_otg_data.phy_of_node = phy_node; 219 grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); 220 221 /* find the grf node */ 222 node = fdt_node_offset_by_compatible(blob, -1, 223 "rockchip,rk3288-grf"); 224 if (node <= 0) { 225 debug("Not found grf device\n"); 226 return -ENODEV; 227 } 228 rk3288_otg_data.regs_phy = grf_phy_offset + 229 fdtdec_get_addr(blob, node, "reg"); 230 231 return dwc2_udc_probe(&rk3288_otg_data); 232 } 233 234 int board_usb_cleanup(int index, enum usb_init_type init) 235 { 236 return 0; 237 } 238 #endif 239 240 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, 241 char * const argv[]) 242 { 243 static const struct { 244 char *name; 245 int id; 246 } clks[] = { 247 { "osc", CLK_OSC }, 248 { "apll", CLK_ARM }, 249 { "dpll", CLK_DDR }, 250 { "cpll", CLK_CODEC }, 251 { "gpll", CLK_GENERAL }, 252 #ifdef CONFIG_ROCKCHIP_RK3036 253 { "mpll", CLK_NEW }, 254 #else 255 { "npll", CLK_NEW }, 256 #endif 257 }; 258 int ret, i; 259 struct udevice *dev; 260 261 ret = rockchip_get_clk(&dev); 262 if (ret) { 263 printf("clk-uclass not found\n"); 264 return 0; 265 } 266 267 for (i = 0; i < ARRAY_SIZE(clks); i++) { 268 struct clk clk; 269 ulong rate; 270 271 clk.id = clks[i].id; 272 ret = clk_request(dev, &clk); 273 if (ret < 0) 274 continue; 275 276 rate = clk_get_rate(&clk); 277 printf("%s: %lu\n", clks[i].name, rate); 278 279 clk_free(&clk); 280 } 281 282 return 0; 283 } 284 285 U_BOOT_CMD( 286 clock, 2, 1, do_clock, 287 "display information about clocks", 288 "" 289 ); 290 291 #define GRF_SOC_CON2 0xff77024c 292 293 int board_early_init_f(void) 294 { 295 struct udevice *pinctrl; 296 struct udevice *dev; 297 int ret; 298 299 /* 300 * This init is done in SPL, but when chain-loading U-Boot SPL will 301 * have been skipped. Allow the clock driver to check if it needs 302 * setting up. 303 */ 304 ret = rockchip_get_clk(&dev); 305 if (ret) { 306 debug("CLK init failed: %d\n", ret); 307 return ret; 308 } 309 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 310 if (ret) { 311 debug("%s: Cannot find pinctrl device\n", __func__); 312 return ret; 313 } 314 315 /* Enable debug UART */ 316 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); 317 if (ret) { 318 debug("%s: Failed to set up console UART\n", __func__); 319 return ret; 320 } 321 rk_setreg(GRF_SOC_CON2, 1 << 0); 322 323 return 0; 324 } 325