1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/cru_rk3288.h> 15 #include <asm/arch/periph.h> 16 #include <asm/arch/pmu_rk3288.h> 17 #include <asm/arch/qos_rk3288.h> 18 #include <asm/arch/boot_mode.h> 19 #include <asm/gpio.h> 20 #include <dm/pinctrl.h> 21 #include <dt-bindings/clock/rk3288-cru.h> 22 #include <power/regulator.h> 23 24 DECLARE_GLOBAL_DATA_PTR; 25 26 __weak int rk_board_late_init(void) 27 { 28 return 0; 29 } 30 31 int rk3288_qos_init(void) 32 { 33 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; 34 /* set vop qos to higher priority */ 35 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); 36 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); 37 38 if (!fdt_node_check_compatible(gd->fdt_blob, 0, 39 "rockchip,rk3288-tinker")) 40 { 41 /* set isp qos to higher priority */ 42 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); 43 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); 44 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); 45 } 46 return 0; 47 } 48 49 static void rk3288_detect_reset_reason(void) 50 { 51 struct rk3288_cru *cru = rockchip_get_cru(); 52 const char *reason; 53 54 if (IS_ERR(cru)) 55 return; 56 57 switch (cru->cru_glb_rst_st) { 58 case GLB_POR_RST: 59 reason = "POR"; 60 break; 61 case FST_GLB_RST_ST: 62 case SND_GLB_RST_ST: 63 reason = "RST"; 64 break; 65 case FST_GLB_TSADC_RST_ST: 66 case SND_GLB_TSADC_RST_ST: 67 reason = "THERMAL"; 68 break; 69 case FST_GLB_WDT_RST_ST: 70 case SND_GLB_WDT_RST_ST: 71 reason = "WDOG"; 72 break; 73 default: 74 reason = "unknown reset"; 75 } 76 77 env_set("reset_reason", reason); 78 79 /* 80 * Clear cru_glb_rst_st, so we can determine the last reset cause 81 * for following resets. 82 */ 83 rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK); 84 } 85 86 int board_late_init(void) 87 { 88 setup_boot_mode(); 89 rk3288_qos_init(); 90 rk3288_detect_reset_reason(); 91 92 return rk_board_late_init(); 93 } 94 95 #if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 96 static int veyron_init(void) 97 { 98 struct udevice *dev; 99 struct clk clk; 100 int ret; 101 102 ret = regulator_get_by_platname("vdd_arm", &dev); 103 if (ret) { 104 debug("Cannot set regulator name\n"); 105 return ret; 106 } 107 108 /* Slowly raise to max CPU voltage to prevent overshoot */ 109 ret = regulator_set_value(dev, 1200000); 110 if (ret) 111 return ret; 112 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ 113 ret = regulator_set_value(dev, 1400000); 114 if (ret) 115 return ret; 116 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ 117 118 ret = rockchip_get_clk(&clk.dev); 119 if (ret) 120 return ret; 121 clk.id = PLL_APLL; 122 ret = clk_set_rate(&clk, 1800000000); 123 if (IS_ERR_VALUE(ret)) 124 return ret; 125 126 return 0; 127 } 128 #endif 129 130 int board_init(void) 131 { 132 #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) 133 struct udevice *pinctrl; 134 int ret; 135 136 /* 137 * We need to implement sdcard iomux here for the further 138 * initlization, otherwise, it'll hit sdcard command sending 139 * timeout exception. 140 */ 141 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 142 if (ret) { 143 debug("%s: Cannot find pinctrl device\n", __func__); 144 goto err; 145 } 146 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); 147 if (ret) { 148 debug("%s: Failed to set up SD card\n", __func__); 149 goto err; 150 } 151 152 return 0; 153 err: 154 printf("board_init: Error %d\n", ret); 155 156 /* No way to report error here */ 157 hang(); 158 159 return -1; 160 #else 161 int ret; 162 163 /* We do some SoC one time setting here */ 164 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { 165 ret = veyron_init(); 166 if (ret) 167 return ret; 168 } 169 170 return 0; 171 #endif 172 } 173 174 #ifndef CONFIG_SYS_DCACHE_OFF 175 void enable_caches(void) 176 { 177 /* Enable D-cache. I-cache is already enabled in start.S */ 178 dcache_enable(); 179 } 180 #endif 181 182 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 183 #include <usb.h> 184 #include <usb/dwc2_udc.h> 185 186 static struct dwc2_plat_otg_data rk3288_otg_data = { 187 .rx_fifo_sz = 512, 188 .np_tx_fifo_sz = 16, 189 .tx_fifo_sz = 128, 190 }; 191 192 int board_usb_init(int index, enum usb_init_type init) 193 { 194 int node, phy_node; 195 const char *mode; 196 bool matched = false; 197 const void *blob = gd->fdt_blob; 198 u32 grf_phy_offset; 199 200 /* find the usb_otg node */ 201 node = fdt_node_offset_by_compatible(blob, -1, 202 "rockchip,rk3288-usb"); 203 204 while (node > 0) { 205 mode = fdt_getprop(blob, node, "dr_mode", NULL); 206 if (mode && strcmp(mode, "otg") == 0) { 207 matched = true; 208 break; 209 } 210 211 node = fdt_node_offset_by_compatible(blob, node, 212 "rockchip,rk3288-usb"); 213 } 214 if (!matched) { 215 debug("Not found usb_otg device\n"); 216 return -ENODEV; 217 } 218 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); 219 220 node = fdtdec_lookup_phandle(blob, node, "phys"); 221 if (node <= 0) { 222 debug("Not found usb phy device\n"); 223 return -ENODEV; 224 } 225 226 phy_node = fdt_parent_offset(blob, node); 227 if (phy_node <= 0) { 228 debug("Not found usb phy device\n"); 229 return -ENODEV; 230 } 231 232 rk3288_otg_data.phy_of_node = phy_node; 233 grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); 234 235 /* find the grf node */ 236 node = fdt_node_offset_by_compatible(blob, -1, 237 "rockchip,rk3288-grf"); 238 if (node <= 0) { 239 debug("Not found grf device\n"); 240 return -ENODEV; 241 } 242 rk3288_otg_data.regs_phy = grf_phy_offset + 243 fdtdec_get_addr(blob, node, "reg"); 244 245 return dwc2_udc_probe(&rk3288_otg_data); 246 } 247 248 int board_usb_cleanup(int index, enum usb_init_type init) 249 { 250 return 0; 251 } 252 #endif 253 254 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, 255 char * const argv[]) 256 { 257 static const struct { 258 char *name; 259 int id; 260 } clks[] = { 261 { "osc", CLK_OSC }, 262 { "apll", CLK_ARM }, 263 { "dpll", CLK_DDR }, 264 { "cpll", CLK_CODEC }, 265 { "gpll", CLK_GENERAL }, 266 #ifdef CONFIG_ROCKCHIP_RK3036 267 { "mpll", CLK_NEW }, 268 #else 269 { "npll", CLK_NEW }, 270 #endif 271 }; 272 int ret, i; 273 struct udevice *dev; 274 275 ret = rockchip_get_clk(&dev); 276 if (ret) { 277 printf("clk-uclass not found\n"); 278 return 0; 279 } 280 281 for (i = 0; i < ARRAY_SIZE(clks); i++) { 282 struct clk clk; 283 ulong rate; 284 285 clk.id = clks[i].id; 286 ret = clk_request(dev, &clk); 287 if (ret < 0) 288 continue; 289 290 rate = clk_get_rate(&clk); 291 printf("%s: %lu\n", clks[i].name, rate); 292 293 clk_free(&clk); 294 } 295 296 return 0; 297 } 298 299 U_BOOT_CMD( 300 clock, 2, 1, do_clock, 301 "display information about clocks", 302 "" 303 ); 304 305 #define GRF_SOC_CON2 0xff77024c 306 307 int board_early_init_f(void) 308 { 309 struct udevice *pinctrl; 310 struct udevice *dev; 311 int ret; 312 313 /* 314 * This init is done in SPL, but when chain-loading U-Boot SPL will 315 * have been skipped. Allow the clock driver to check if it needs 316 * setting up. 317 */ 318 ret = rockchip_get_clk(&dev); 319 if (ret) { 320 debug("CLK init failed: %d\n", ret); 321 return ret; 322 } 323 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 324 if (ret) { 325 debug("%s: Cannot find pinctrl device\n", __func__); 326 return ret; 327 } 328 329 /* Enable debug UART */ 330 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); 331 if (ret) { 332 debug("%s: Failed to set up console UART\n", __func__); 333 return ret; 334 } 335 rk_setreg(GRF_SOC_CON2, 1 << 0); 336 337 return 0; 338 } 339