1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/periph.h> 15 #include <asm/arch/pmu_rk3288.h> 16 #include <asm/arch/boot_mode.h> 17 #include <asm/gpio.h> 18 #include <dm/pinctrl.h> 19 #include <dt-bindings/clock/rk3288-cru.h> 20 #include <power/regulator.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 #define PMU_BASE 0xff730000 25 26 static void setup_boot_mode(void) 27 { 28 struct rk3288_pmu *const pmu = (void *)PMU_BASE; 29 int boot_mode = readl(&pmu->sys_reg[0]); 30 31 debug("boot mode %x.\n", boot_mode); 32 33 /* Clear boot mode */ 34 writel(BOOT_NORMAL, &pmu->sys_reg[0]); 35 36 switch (boot_mode) { 37 case BOOT_FASTBOOT: 38 printf("enter fastboot!\n"); 39 setenv("preboot", "setenv preboot; fastboot usb0"); 40 break; 41 case BOOT_UMS: 42 printf("enter UMS!\n"); 43 setenv("preboot", "setenv preboot; if mmc dev 0;" 44 "then ums mmc 0; else ums mmc 1;fi"); 45 break; 46 } 47 } 48 49 __weak int rk_board_late_init(void) 50 { 51 return 0; 52 } 53 54 int board_late_init(void) 55 { 56 setup_boot_mode(); 57 58 return rk_board_late_init(); 59 } 60 61 #ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 62 static int veyron_init(void) 63 { 64 struct udevice *dev; 65 struct clk clk; 66 int ret; 67 68 ret = regulator_get_by_platname("vdd_arm", &dev); 69 if (ret) 70 return ret; 71 72 /* Slowly raise to max CPU voltage to prevent overshoot */ 73 ret = regulator_set_value(dev, 1200000); 74 if (ret) 75 return ret; 76 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ 77 ret = regulator_set_value(dev, 1400000); 78 if (ret) 79 return ret; 80 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ 81 82 ret = rockchip_get_clk(&clk.dev); 83 if (ret) 84 return ret; 85 clk.id = PLL_APLL; 86 ret = clk_set_rate(&clk, 1800000000); 87 if (IS_ERR_VALUE(ret)) 88 return ret; 89 90 return 0; 91 } 92 #endif 93 94 int board_init(void) 95 { 96 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 97 struct udevice *pinctrl; 98 int ret; 99 100 /* 101 * We need to implement sdcard iomux here for the further 102 * initlization, otherwise, it'll hit sdcard command sending 103 * timeout exception. 104 */ 105 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 106 if (ret) { 107 debug("%s: Cannot find pinctrl device\n", __func__); 108 goto err; 109 } 110 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); 111 if (ret) { 112 debug("%s: Failed to set up SD card\n", __func__); 113 goto err; 114 } 115 116 return 0; 117 err: 118 printf("board_init: Error %d\n", ret); 119 120 /* No way to report error here */ 121 hang(); 122 123 return -1; 124 #else 125 int ret; 126 127 /* We do some SoC one time setting here */ 128 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { 129 ret = veyron_init(); 130 if (ret) 131 return ret; 132 } 133 134 return 0; 135 #endif 136 } 137 138 int dram_init(void) 139 { 140 struct ram_info ram; 141 struct udevice *dev; 142 int ret; 143 144 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 145 if (ret) { 146 debug("DRAM init failed: %d\n", ret); 147 return ret; 148 } 149 ret = ram_get_info(dev, &ram); 150 if (ret) { 151 debug("Cannot get DRAM size: %d\n", ret); 152 return ret; 153 } 154 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); 155 gd->ram_size = ram.size; 156 157 return 0; 158 } 159 160 #ifndef CONFIG_SYS_DCACHE_OFF 161 void enable_caches(void) 162 { 163 /* Enable D-cache. I-cache is already enabled in start.S */ 164 dcache_enable(); 165 } 166 #endif 167 168 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 169 #include <usb.h> 170 #include <usb/dwc2_udc.h> 171 172 static struct dwc2_plat_otg_data rk3288_otg_data = { 173 .rx_fifo_sz = 512, 174 .np_tx_fifo_sz = 16, 175 .tx_fifo_sz = 128, 176 }; 177 178 int board_usb_init(int index, enum usb_init_type init) 179 { 180 int node, phy_node; 181 const char *mode; 182 bool matched = false; 183 const void *blob = gd->fdt_blob; 184 u32 grf_phy_offset; 185 186 /* find the usb_otg node */ 187 node = fdt_node_offset_by_compatible(blob, -1, 188 "rockchip,rk3288-usb"); 189 190 while (node > 0) { 191 mode = fdt_getprop(blob, node, "dr_mode", NULL); 192 if (mode && strcmp(mode, "otg") == 0) { 193 matched = true; 194 break; 195 } 196 197 node = fdt_node_offset_by_compatible(blob, node, 198 "rockchip,rk3288-usb"); 199 } 200 if (!matched) { 201 debug("Not found usb_otg device\n"); 202 return -ENODEV; 203 } 204 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); 205 206 node = fdtdec_lookup_phandle(blob, node, "phys"); 207 if (node <= 0) { 208 debug("Not found usb phy device\n"); 209 return -ENODEV; 210 } 211 212 phy_node = fdt_parent_offset(blob, node); 213 if (phy_node <= 0) { 214 debug("Not found usb phy device\n"); 215 return -ENODEV; 216 } 217 218 rk3288_otg_data.phy_of_node = phy_node; 219 grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); 220 221 /* find the grf node */ 222 node = fdt_node_offset_by_compatible(blob, -1, 223 "rockchip,rk3288-grf"); 224 if (node <= 0) { 225 debug("Not found grf device\n"); 226 return -ENODEV; 227 } 228 rk3288_otg_data.regs_phy = grf_phy_offset + 229 fdtdec_get_addr(blob, node, "reg"); 230 231 return dwc2_udc_probe(&rk3288_otg_data); 232 } 233 234 int board_usb_cleanup(int index, enum usb_init_type init) 235 { 236 return 0; 237 } 238 #endif 239 240 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, 241 char * const argv[]) 242 { 243 static const struct { 244 char *name; 245 int id; 246 } clks[] = { 247 { "osc", CLK_OSC }, 248 { "apll", CLK_ARM }, 249 { "dpll", CLK_DDR }, 250 { "cpll", CLK_CODEC }, 251 { "gpll", CLK_GENERAL }, 252 #ifdef CONFIG_ROCKCHIP_RK3036 253 { "mpll", CLK_NEW }, 254 #else 255 { "npll", CLK_NEW }, 256 #endif 257 }; 258 int ret, i; 259 struct udevice *dev; 260 261 ret = rockchip_get_clk(&dev); 262 if (ret) { 263 printf("clk-uclass not found\n"); 264 return 0; 265 } 266 267 for (i = 0; i < ARRAY_SIZE(clks); i++) { 268 struct clk clk; 269 ulong rate; 270 271 clk.id = clks[i].id; 272 ret = clk_request(dev, &clk); 273 if (ret < 0) 274 continue; 275 276 rate = clk_get_rate(&clk); 277 printf("%s: %lu\n", clks[i].name, rate); 278 279 clk_free(&clk); 280 } 281 282 return 0; 283 } 284 285 U_BOOT_CMD( 286 clock, 2, 1, do_clock, 287 "display information about clocks", 288 "" 289 ); 290