1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <ram.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/periph.h> 15 #include <asm/arch/pmu_rk3288.h> 16 #include <asm/arch/qos_rk3288.h> 17 #include <asm/arch/boot_mode.h> 18 #include <asm/gpio.h> 19 #include <dm/pinctrl.h> 20 #include <dt-bindings/clock/rk3288-cru.h> 21 #include <power/regulator.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 #define PMU_BASE 0xff730000 26 27 static void setup_boot_mode(void) 28 { 29 struct rk3288_pmu *const pmu = (void *)PMU_BASE; 30 int boot_mode = readl(&pmu->sys_reg[0]); 31 32 debug("boot mode %x.\n", boot_mode); 33 34 /* Clear boot mode */ 35 writel(BOOT_NORMAL, &pmu->sys_reg[0]); 36 37 switch (boot_mode) { 38 case BOOT_FASTBOOT: 39 printf("enter fastboot!\n"); 40 setenv("preboot", "setenv preboot; fastboot usb0"); 41 break; 42 case BOOT_UMS: 43 printf("enter UMS!\n"); 44 setenv("preboot", "setenv preboot; if mmc dev 0;" 45 "then ums mmc 0; else ums mmc 1;fi"); 46 break; 47 } 48 } 49 50 __weak int rk_board_late_init(void) 51 { 52 return 0; 53 } 54 55 int rk3288_qos_init(void) 56 { 57 int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; 58 /* set vop qos to higher priority */ 59 writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); 60 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); 61 62 if (!fdt_node_check_compatible(gd->fdt_blob, 0, 63 "rockchip,rk3288-tinker")) 64 { 65 /* set isp qos to higher priority */ 66 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); 67 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); 68 writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); 69 } 70 return 0; 71 } 72 73 int board_late_init(void) 74 { 75 setup_boot_mode(); 76 rk3288_qos_init(); 77 78 return rk_board_late_init(); 79 } 80 81 #ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 82 static int veyron_init(void) 83 { 84 struct udevice *dev; 85 struct clk clk; 86 int ret; 87 88 ret = regulator_get_by_platname("vdd_arm", &dev); 89 if (ret) { 90 debug("Cannot set regulator name\n"); 91 return ret; 92 } 93 94 /* Slowly raise to max CPU voltage to prevent overshoot */ 95 ret = regulator_set_value(dev, 1200000); 96 if (ret) 97 return ret; 98 udelay(175); /* Must wait for voltage to stabilize, 2mV/us */ 99 ret = regulator_set_value(dev, 1400000); 100 if (ret) 101 return ret; 102 udelay(100); /* Must wait for voltage to stabilize, 2mV/us */ 103 104 ret = rockchip_get_clk(&clk.dev); 105 if (ret) 106 return ret; 107 clk.id = PLL_APLL; 108 ret = clk_set_rate(&clk, 1800000000); 109 if (IS_ERR_VALUE(ret)) 110 return ret; 111 112 return 0; 113 } 114 #endif 115 116 int board_init(void) 117 { 118 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM 119 struct udevice *pinctrl; 120 int ret; 121 122 /* 123 * We need to implement sdcard iomux here for the further 124 * initlization, otherwise, it'll hit sdcard command sending 125 * timeout exception. 126 */ 127 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 128 if (ret) { 129 debug("%s: Cannot find pinctrl device\n", __func__); 130 goto err; 131 } 132 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); 133 if (ret) { 134 debug("%s: Failed to set up SD card\n", __func__); 135 goto err; 136 } 137 138 return 0; 139 err: 140 printf("board_init: Error %d\n", ret); 141 142 /* No way to report error here */ 143 hang(); 144 145 return -1; 146 #else 147 int ret; 148 149 /* We do some SoC one time setting here */ 150 if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) { 151 ret = veyron_init(); 152 if (ret) 153 return ret; 154 } 155 156 return 0; 157 #endif 158 } 159 160 int dram_init(void) 161 { 162 struct ram_info ram; 163 struct udevice *dev; 164 int ret; 165 166 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 167 if (ret) { 168 debug("DRAM init failed: %d\n", ret); 169 return ret; 170 } 171 ret = ram_get_info(dev, &ram); 172 if (ret) { 173 debug("Cannot get DRAM size: %d\n", ret); 174 return ret; 175 } 176 debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); 177 gd->ram_size = ram.size; 178 179 return 0; 180 } 181 182 #ifndef CONFIG_SYS_DCACHE_OFF 183 void enable_caches(void) 184 { 185 /* Enable D-cache. I-cache is already enabled in start.S */ 186 dcache_enable(); 187 } 188 #endif 189 190 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) 191 #include <usb.h> 192 #include <usb/dwc2_udc.h> 193 194 static struct dwc2_plat_otg_data rk3288_otg_data = { 195 .rx_fifo_sz = 512, 196 .np_tx_fifo_sz = 16, 197 .tx_fifo_sz = 128, 198 }; 199 200 int board_usb_init(int index, enum usb_init_type init) 201 { 202 int node, phy_node; 203 const char *mode; 204 bool matched = false; 205 const void *blob = gd->fdt_blob; 206 u32 grf_phy_offset; 207 208 /* find the usb_otg node */ 209 node = fdt_node_offset_by_compatible(blob, -1, 210 "rockchip,rk3288-usb"); 211 212 while (node > 0) { 213 mode = fdt_getprop(blob, node, "dr_mode", NULL); 214 if (mode && strcmp(mode, "otg") == 0) { 215 matched = true; 216 break; 217 } 218 219 node = fdt_node_offset_by_compatible(blob, node, 220 "rockchip,rk3288-usb"); 221 } 222 if (!matched) { 223 debug("Not found usb_otg device\n"); 224 return -ENODEV; 225 } 226 rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); 227 228 node = fdtdec_lookup_phandle(blob, node, "phys"); 229 if (node <= 0) { 230 debug("Not found usb phy device\n"); 231 return -ENODEV; 232 } 233 234 phy_node = fdt_parent_offset(blob, node); 235 if (phy_node <= 0) { 236 debug("Not found usb phy device\n"); 237 return -ENODEV; 238 } 239 240 rk3288_otg_data.phy_of_node = phy_node; 241 grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); 242 243 /* find the grf node */ 244 node = fdt_node_offset_by_compatible(blob, -1, 245 "rockchip,rk3288-grf"); 246 if (node <= 0) { 247 debug("Not found grf device\n"); 248 return -ENODEV; 249 } 250 rk3288_otg_data.regs_phy = grf_phy_offset + 251 fdtdec_get_addr(blob, node, "reg"); 252 253 return dwc2_udc_probe(&rk3288_otg_data); 254 } 255 256 int board_usb_cleanup(int index, enum usb_init_type init) 257 { 258 return 0; 259 } 260 #endif 261 262 static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, 263 char * const argv[]) 264 { 265 static const struct { 266 char *name; 267 int id; 268 } clks[] = { 269 { "osc", CLK_OSC }, 270 { "apll", CLK_ARM }, 271 { "dpll", CLK_DDR }, 272 { "cpll", CLK_CODEC }, 273 { "gpll", CLK_GENERAL }, 274 #ifdef CONFIG_ROCKCHIP_RK3036 275 { "mpll", CLK_NEW }, 276 #else 277 { "npll", CLK_NEW }, 278 #endif 279 }; 280 int ret, i; 281 struct udevice *dev; 282 283 ret = rockchip_get_clk(&dev); 284 if (ret) { 285 printf("clk-uclass not found\n"); 286 return 0; 287 } 288 289 for (i = 0; i < ARRAY_SIZE(clks); i++) { 290 struct clk clk; 291 ulong rate; 292 293 clk.id = clks[i].id; 294 ret = clk_request(dev, &clk); 295 if (ret < 0) 296 continue; 297 298 rate = clk_get_rate(&clk); 299 printf("%s: %lu\n", clks[i].name, rate); 300 301 clk_free(&clk); 302 } 303 304 return 0; 305 } 306 307 U_BOOT_CMD( 308 clock, 2, 1, do_clock, 309 "display information about clocks", 310 "" 311 ); 312 313 #define GRF_SOC_CON2 0xff77024c 314 315 int board_early_init_f(void) 316 { 317 struct udevice *pinctrl; 318 struct udevice *dev; 319 int ret; 320 321 /* 322 * This init is done in SPL, but when chain-loading U-Boot SPL will 323 * have been skipped. Allow the clock driver to check if it needs 324 * setting up. 325 */ 326 ret = rockchip_get_clk(&dev); 327 if (ret) { 328 debug("CLK init failed: %d\n", ret); 329 return ret; 330 } 331 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 332 if (ret) { 333 debug("%s: Cannot find pinctrl device\n", __func__); 334 return ret; 335 } 336 337 /* Enable debug UART */ 338 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); 339 if (ret) { 340 debug("%s: Failed to set up console UART\n", __func__); 341 return ret; 342 } 343 rk_setreg(GRF_SOC_CON2, 1 << 0); 344 345 return 0; 346 } 347