1 /*
2  * (C) Copyright 2015 Google, Inc
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <debug_uart.h>
9 #include <dm.h>
10 #include <fdtdec.h>
11 #include <led.h>
12 #include <malloc.h>
13 #include <ram.h>
14 #include <spl.h>
15 #include <asm/gpio.h>
16 #include <asm/io.h>
17 #include <asm/arch/bootrom.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/hardware.h>
20 #include <asm/arch/periph.h>
21 #include <asm/arch/sdram.h>
22 #include <asm/arch/timer.h>
23 #include <dm/pinctrl.h>
24 #include <dm/root.h>
25 #include <dm/test.h>
26 #include <dm/util.h>
27 #include <power/regulator.h>
28 
29 DECLARE_GLOBAL_DATA_PTR;
30 
31 u32 spl_boot_device(void)
32 {
33 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
34 	const void *blob = gd->fdt_blob;
35 	struct udevice *dev;
36 	const char *bootdev;
37 	int node;
38 	int ret;
39 
40 	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
41 	debug("Boot device %s\n", bootdev);
42 	if (!bootdev)
43 		goto fallback;
44 
45 	node = fdt_path_offset(blob, bootdev);
46 	if (node < 0) {
47 		debug("node=%d\n", node);
48 		goto fallback;
49 	}
50 	ret = device_get_global_by_of_offset(node, &dev);
51 	if (ret) {
52 		debug("device at node %s/%d not found: %d\n", bootdev, node,
53 		      ret);
54 		goto fallback;
55 	}
56 	debug("Found device %s\n", dev->name);
57 	switch (device_get_uclass_id(dev)) {
58 	case UCLASS_SPI_FLASH:
59 		return BOOT_DEVICE_SPI;
60 	case UCLASS_MMC:
61 		return BOOT_DEVICE_MMC1;
62 	default:
63 		debug("Booting from device uclass '%s' not supported\n",
64 		      dev_get_uclass_name(dev));
65 	}
66 
67 fallback:
68 #elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
69 		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
70 		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
71 	return BOOT_DEVICE_SPI;
72 #endif
73 	return BOOT_DEVICE_MMC1;
74 }
75 
76 u32 spl_boot_mode(const u32 boot_device)
77 {
78 	return MMCSD_MODE_RAW;
79 }
80 
81 /* read L2 control register (L2CTLR) */
82 static inline uint32_t read_l2ctlr(void)
83 {
84 	uint32_t val = 0;
85 
86 	asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
87 
88 	return val;
89 }
90 
91 /* write L2 control register (L2CTLR) */
92 static inline void write_l2ctlr(uint32_t val)
93 {
94 	/*
95 	 * Note: L2CTLR can only be written when the L2 memory system
96 	 * is idle, ie before the MMU is enabled.
97 	 */
98 	asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
99 	isb();
100 }
101 
102 static void configure_l2ctlr(void)
103 {
104 	uint32_t l2ctlr;
105 
106 	l2ctlr = read_l2ctlr();
107 	l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
108 
109 	/*
110 	* Data RAM write latency: 2 cycles
111 	* Data RAM read latency: 2 cycles
112 	* Data RAM setup latency: 1 cycle
113 	* Tag RAM write latency: 1 cycle
114 	* Tag RAM read latency: 1 cycle
115 	* Tag RAM setup latency: 1 cycle
116 	*/
117 	l2ctlr |= (1 << 3 | 1 << 0);
118 	write_l2ctlr(l2ctlr);
119 }
120 
121 #ifdef CONFIG_SPL_MMC_SUPPORT
122 static int configure_emmc(struct udevice *pinctrl)
123 {
124 #if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
125 
126 	struct gpio_desc desc;
127 	int ret;
128 
129 	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
130 
131 	/*
132 	 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
133 	 * use the EMMC_PWREN setting.
134 	 */
135 	ret = dm_gpio_lookup_name("D9", &desc);
136 	if (ret) {
137 		debug("gpio ret=%d\n", ret);
138 		return ret;
139 	}
140 	ret = dm_gpio_request(&desc, "emmc_pwren");
141 	if (ret) {
142 		debug("gpio_request ret=%d\n", ret);
143 		return ret;
144 	}
145 	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
146 	if (ret) {
147 		debug("gpio dir ret=%d\n", ret);
148 		return ret;
149 	}
150 	ret = dm_gpio_set_value(&desc, 1);
151 	if (ret) {
152 		debug("gpio value ret=%d\n", ret);
153 		return ret;
154 	}
155 #endif
156 	return 0;
157 }
158 #endif
159 
160 void board_init_f(ulong dummy)
161 {
162 	struct udevice *pinctrl;
163 	struct udevice *dev;
164 	int ret;
165 
166 	/* Example code showing how to enable the debug UART on RK3288 */
167 #ifdef EARLY_UART
168 #include <asm/arch/grf_rk3288.h>
169 	/* Enable early UART on the RK3288 */
170 #define GRF_BASE	0xff770000
171 	struct rk3288_grf * const grf = (void *)GRF_BASE;
172 
173 	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
174 		     GPIO7C6_MASK << GPIO7C6_SHIFT,
175 		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
176 		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
177 	/*
178 	 * Debug UART can be used from here if required:
179 	 *
180 	 * debug_uart_init();
181 	 * printch('a');
182 	 * printhex8(0x1234);
183 	 * printascii("string");
184 	 */
185 	debug_uart_init();
186 #endif
187 
188 	ret = spl_early_init();
189 	if (ret) {
190 		debug("spl_early_init() failed: %d\n", ret);
191 		hang();
192 	}
193 
194 	rockchip_timer_init();
195 	configure_l2ctlr();
196 
197 	ret = rockchip_get_clk(&dev);
198 	if (ret) {
199 		debug("CLK init failed: %d\n", ret);
200 		return;
201 	}
202 
203 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
204 	if (ret) {
205 		debug("Pinctrl init failed: %d\n", ret);
206 		return;
207 	}
208 
209 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
210 	if (ret) {
211 		debug("DRAM init failed: %d\n", ret);
212 		return;
213 	}
214 #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
215 	back_to_bootrom();
216 #endif
217 }
218 
219 static int setup_led(void)
220 {
221 #ifdef CONFIG_SPL_LED
222 	struct udevice *dev;
223 	char *led_name;
224 	int ret;
225 
226 	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
227 	if (!led_name)
228 		return 0;
229 	ret = led_get_by_label(led_name, &dev);
230 	if (ret) {
231 		debug("%s: get=%d\n", __func__, ret);
232 		return ret;
233 	}
234 	ret = led_set_on(dev, 1);
235 	if (ret)
236 		return ret;
237 #endif
238 
239 	return 0;
240 }
241 
242 void spl_board_init(void)
243 {
244 	struct udevice *pinctrl;
245 	int ret;
246 
247 	ret = setup_led();
248 
249 	if (ret) {
250 		debug("LED ret=%d\n", ret);
251 		hang();
252 	}
253 
254 	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
255 	if (ret) {
256 		debug("%s: Cannot find pinctrl device\n", __func__);
257 		goto err;
258 	}
259 
260 #ifdef CONFIG_SPL_MMC_SUPPORT
261 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
262 	if (ret) {
263 		debug("%s: Failed to set up SD card\n", __func__);
264 		goto err;
265 	}
266 	ret = configure_emmc(pinctrl);
267 	if (ret) {
268 		debug("%s: Failed to set up eMMC\n", __func__);
269 		goto err;
270 	}
271 #endif
272 
273 	/* Enable debug UART */
274 	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
275 	if (ret) {
276 		debug("%s: Failed to set up console UART\n", __func__);
277 		goto err;
278 	}
279 
280 	preloader_console_init();
281 #ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
282 	back_to_bootrom();
283 #endif
284 	return;
285 err:
286 	printf("spl_board_init: Error %d\n", ret);
287 
288 	/* No way to report error here */
289 	hang();
290 }
291