1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <debug_uart.h> 9 #include <dm.h> 10 #include <fdtdec.h> 11 #include <led.h> 12 #include <malloc.h> 13 #include <ram.h> 14 #include <spl.h> 15 #include <asm/gpio.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/periph.h> 20 #include <asm/arch/sdram.h> 21 #include <asm/arch/timer.h> 22 #include <dm/pinctrl.h> 23 #include <dm/root.h> 24 #include <dm/test.h> 25 #include <dm/util.h> 26 #include <power/regulator.h> 27 28 DECLARE_GLOBAL_DATA_PTR; 29 30 u32 spl_boot_device(void) 31 { 32 const void *blob = gd->fdt_blob; 33 struct udevice *dev; 34 const char *bootdev; 35 int node; 36 int ret; 37 38 bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); 39 debug("Boot device %s\n", bootdev); 40 if (!bootdev) 41 goto fallback; 42 43 node = fdt_path_offset(blob, bootdev); 44 if (node < 0) { 45 debug("node=%d\n", node); 46 goto fallback; 47 } 48 ret = device_get_global_by_of_offset(node, &dev); 49 if (ret) { 50 debug("device at node %s/%d not found: %d\n", bootdev, node, 51 ret); 52 goto fallback; 53 } 54 debug("Found device %s\n", dev->name); 55 switch (device_get_uclass_id(dev)) { 56 case UCLASS_SPI_FLASH: 57 return BOOT_DEVICE_SPI; 58 case UCLASS_MMC: 59 return BOOT_DEVICE_MMC1; 60 default: 61 debug("Booting from device uclass '%s' not supported\n", 62 dev_get_uclass_name(dev)); 63 } 64 65 fallback: 66 return BOOT_DEVICE_MMC1; 67 } 68 69 u32 spl_boot_mode(void) 70 { 71 return MMCSD_MODE_RAW; 72 } 73 74 /* read L2 control register (L2CTLR) */ 75 static inline uint32_t read_l2ctlr(void) 76 { 77 uint32_t val = 0; 78 79 asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); 80 81 return val; 82 } 83 84 /* write L2 control register (L2CTLR) */ 85 static inline void write_l2ctlr(uint32_t val) 86 { 87 /* 88 * Note: L2CTLR can only be written when the L2 memory system 89 * is idle, ie before the MMU is enabled. 90 */ 91 asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); 92 isb(); 93 } 94 95 static void configure_l2ctlr(void) 96 { 97 uint32_t l2ctlr; 98 99 l2ctlr = read_l2ctlr(); 100 l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ 101 102 /* 103 * Data RAM write latency: 2 cycles 104 * Data RAM read latency: 2 cycles 105 * Data RAM setup latency: 1 cycle 106 * Tag RAM write latency: 1 cycle 107 * Tag RAM read latency: 1 cycle 108 * Tag RAM setup latency: 1 cycle 109 */ 110 l2ctlr |= (1 << 3 | 1 << 0); 111 write_l2ctlr(l2ctlr); 112 } 113 114 static int configure_emmc(struct udevice *pinctrl) 115 { 116 struct gpio_desc desc; 117 int ret; 118 119 pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC); 120 121 /* 122 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps 123 * use the EMMC_PWREN setting. 124 */ 125 ret = dm_gpio_lookup_name("D9", &desc); 126 if (ret) { 127 debug("gpio ret=%d\n", ret); 128 return ret; 129 } 130 ret = dm_gpio_request(&desc, "emmc_pwren"); 131 if (ret) { 132 debug("gpio_request ret=%d\n", ret); 133 return ret; 134 } 135 ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); 136 if (ret) { 137 debug("gpio dir ret=%d\n", ret); 138 return ret; 139 } 140 ret = dm_gpio_set_value(&desc, 1); 141 if (ret) { 142 debug("gpio value ret=%d\n", ret); 143 return ret; 144 } 145 146 return 0; 147 } 148 149 void board_init_f(ulong dummy) 150 { 151 struct udevice *pinctrl; 152 struct udevice *dev; 153 int ret; 154 155 /* Example code showing how to enable the debug UART on RK3288 */ 156 #ifdef EARLY_UART 157 #include <asm/arch/grf_rk3288.h> 158 /* Enable early UART on the RK3288 */ 159 #define GRF_BASE 0xff770000 160 struct rk3288_grf * const grf = (void *)GRF_BASE; 161 162 rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | 163 GPIO7C6_MASK << GPIO7C6_SHIFT, 164 GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | 165 GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); 166 /* 167 * Debug UART can be used from here if required: 168 * 169 * debug_uart_init(); 170 * printch('a'); 171 * printhex8(0x1234); 172 * printascii("string"); 173 */ 174 debug_uart_init(); 175 #endif 176 177 ret = spl_init(); 178 if (ret) { 179 debug("spl_init() failed: %d\n", ret); 180 hang(); 181 } 182 183 rockchip_timer_init(); 184 configure_l2ctlr(); 185 186 ret = uclass_get_device(UCLASS_CLK, 0, &dev); 187 if (ret) { 188 debug("CLK init failed: %d\n", ret); 189 return; 190 } 191 192 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 193 if (ret) { 194 debug("Pinctrl init failed: %d\n", ret); 195 return; 196 } 197 198 ret = uclass_get_device(UCLASS_RAM, 0, &dev); 199 if (ret) { 200 debug("DRAM init failed: %d\n", ret); 201 return; 202 } 203 } 204 205 static int setup_led(void) 206 { 207 #ifdef CONFIG_SPL_LED 208 struct udevice *dev; 209 char *led_name; 210 int ret; 211 212 led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); 213 if (!led_name) 214 return 0; 215 ret = led_get_by_label(led_name, &dev); 216 if (ret) { 217 debug("%s: get=%d\n", __func__, ret); 218 return ret; 219 } 220 ret = led_set_on(dev, 1); 221 if (ret) 222 return ret; 223 #endif 224 225 return 0; 226 } 227 228 void spl_board_init(void) 229 { 230 struct udevice *pinctrl; 231 int ret; 232 233 ret = setup_led(); 234 235 if (ret) { 236 debug("LED ret=%d\n", ret); 237 hang(); 238 } 239 240 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 241 if (ret) { 242 debug("%s: Cannot find pinctrl device\n", __func__); 243 goto err; 244 } 245 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); 246 if (ret) { 247 debug("%s: Failed to set up SD card\n", __func__); 248 goto err; 249 } 250 ret = configure_emmc(pinctrl); 251 if (ret) { 252 debug("%s: Failed to set up eMMC\n", __func__); 253 goto err; 254 } 255 256 /* Enable debug UART */ 257 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); 258 if (ret) { 259 debug("%s: Failed to set up console UART\n", __func__); 260 goto err; 261 } 262 263 preloader_console_init(); 264 return; 265 err: 266 printf("spl_board_init: Error %d\n", ret); 267 268 /* No way to report error here */ 269 hang(); 270 } 271