1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <ram.h>
10 #include <syscon.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/periph.h>
14 #include <asm/arch/grf_rk322x.h>
15 #include <asm/arch/boot_mode.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 __weak int rk_board_late_init(void)
20 {
21 	return 0;
22 }
23 
24 int board_late_init(void)
25 {
26 	setup_boot_mode();
27 
28 	return rk_board_late_init();
29 }
30 
31 int board_init(void)
32 {
33 #include <asm/arch/grf_rk322x.h>
34 	/* Enable early UART2 channel 1 on the RK322x */
35 #define GRF_BASE	0x11000000
36 	struct rk322x_grf * const grf = (void *)GRF_BASE;
37 
38 	rk_clrsetreg(&grf->gpio1b_iomux,
39 		     GPIO1B1_MASK | GPIO1B2_MASK,
40 		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
41 		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
42 	/* Set channel C as UART2 input */
43 	rk_clrsetreg(&grf->con_iomux,
44 		     CON_IOMUX_UART2SEL_MASK,
45 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
46 
47 	/*
48 	* The integrated macphy is enabled by default, disable it
49 	* for saving power consuming.
50 	*/
51 	rk_clrsetreg(&grf->macphy_con[0],
52 		     MACPHY_CFG_ENABLE_MASK,
53 		     0 << MACPHY_CFG_ENABLE_SHIFT);
54 
55 	return 0;
56 }
57 
58 int dram_init_banksize(void)
59 {
60 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
61 	gd->bd->bi_dram[0].size = 0x8400000;
62 	/* Reserve 0x200000 for OPTEE */
63 	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
64 				+ gd->bd->bi_dram[0].size + 0x200000;
65 	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
66 				+ gd->ram_size - gd->bd->bi_dram[1].start;
67 
68 	return 0;
69 }
70 
71 #ifndef CONFIG_SYS_DCACHE_OFF
72 void enable_caches(void)
73 {
74 	/* Enable D-cache. I-cache is already enabled in start.S */
75 	dcache_enable();
76 }
77 #endif
78 
79 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
80 #include <usb.h>
81 #include <usb/dwc2_udc.h>
82 
83 static struct dwc2_plat_otg_data rk322x_otg_data = {
84 	.rx_fifo_sz	= 512,
85 	.np_tx_fifo_sz	= 16,
86 	.tx_fifo_sz	= 128,
87 };
88 
89 int board_usb_init(int index, enum usb_init_type init)
90 {
91 	int node;
92 	const char *mode;
93 	bool matched = false;
94 	const void *blob = gd->fdt_blob;
95 
96 	/* find the usb_otg node */
97 	node = fdt_node_offset_by_compatible(blob, -1,
98 					"rockchip,rk3288-usb");
99 
100 	while (node > 0) {
101 		mode = fdt_getprop(blob, node, "dr_mode", NULL);
102 		if (mode && strcmp(mode, "otg") == 0) {
103 			matched = true;
104 			break;
105 		}
106 
107 		node = fdt_node_offset_by_compatible(blob, node,
108 					"rockchip,rk3288-usb");
109 	}
110 	if (!matched) {
111 		debug("Not found usb_otg device\n");
112 		return -ENODEV;
113 	}
114 	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
115 
116 	return dwc2_udc_probe(&rk322x_otg_data);
117 }
118 
119 int board_usb_cleanup(int index, enum usb_init_type init)
120 {
121 	return 0;
122 }
123 #endif
124 
125 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
126 int fb_set_reboot_flag(void)
127 {
128 	struct rk322x_grf *grf;
129 
130 	printf("Setting reboot to fastboot flag ...\n");
131 	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
132 	/* Set boot mode to fastboot */
133 	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
134 
135 	return 0;
136 }
137 #endif
138