1 /*
2  * (C) Copyright 2017 Rockchip Electronics Co., Ltd.
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <clk.h>
8 #include <dm.h>
9 #include <ram.h>
10 #include <syscon.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/periph.h>
14 #include <asm/arch/grf_rk322x.h>
15 #include <asm/arch/boot_mode.h>
16 
17 DECLARE_GLOBAL_DATA_PTR;
18 
19 __weak int rk_board_late_init(void)
20 {
21 	return 0;
22 }
23 
24 int board_late_init(void)
25 {
26 	setup_boot_mode();
27 
28 	return rk_board_late_init();
29 }
30 
31 int board_init(void)
32 {
33 #include <asm/arch/grf_rk322x.h>
34 	/* Enable early UART2 channel 1 on the RK322x */
35 #define GRF_BASE	0x11000000
36 	struct rk322x_grf * const grf = (void *)GRF_BASE;
37 	enum {
38 		GPIO1B2_SHIFT		= 4,
39 		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
40 		GPIO1B2_GPIO		= 0,
41 		GPIO1B2_UART21_SIN,
42 
43 		GPIO1B1_SHIFT		= 2,
44 		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
45 		GPIO1B1_GPIO            = 0,
46 		GPIO1B1_UART1_SOUT,
47 		GPIO1B1_UART21_SOUT,
48 	};
49 	enum {
50 		CON_IOMUX_UART2SEL_SHIFT= 8,
51 		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
52 		CON_IOMUX_UART2SEL_2	= 0,
53 		CON_IOMUX_UART2SEL_21,
54 	};
55 
56 	rk_clrsetreg(&grf->gpio1b_iomux,
57 		     GPIO1B1_MASK | GPIO1B2_MASK,
58 		     GPIO1B2_UART21_SIN << GPIO1B2_SHIFT |
59 		     GPIO1B1_UART21_SOUT << GPIO1B1_SHIFT);
60 	/* Set channel C as UART2 input */
61 	rk_clrsetreg(&grf->con_iomux,
62 		     CON_IOMUX_UART2SEL_MASK,
63 		     CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT);
64 
65 	/*
66 	* The integrated macphy is enabled by default, disable it
67 	* for saving power consuming.
68 	*/
69 	rk_clrsetreg(&grf->macphy_con[0],
70 		     MACPHY_CFG_ENABLE_MASK,
71 		     0 << MACPHY_CFG_ENABLE_SHIFT);
72 
73 	return 0;
74 }
75 
76 int dram_init_banksize(void)
77 {
78 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
79 	gd->bd->bi_dram[0].size = 0x8400000;
80 	/* Reserve 0x200000 for OPTEE */
81 	gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
82 				+ gd->bd->bi_dram[0].size + 0x200000;
83 	gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
84 				+ gd->ram_size - gd->bd->bi_dram[1].start;
85 
86 	return 0;
87 }
88 
89 #ifndef CONFIG_SYS_DCACHE_OFF
90 void enable_caches(void)
91 {
92 	/* Enable D-cache. I-cache is already enabled in start.S */
93 	dcache_enable();
94 }
95 #endif
96 
97 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
98 #include <usb.h>
99 #include <usb/dwc2_udc.h>
100 
101 static struct dwc2_plat_otg_data rk322x_otg_data = {
102 	.rx_fifo_sz	= 512,
103 	.np_tx_fifo_sz	= 16,
104 	.tx_fifo_sz	= 128,
105 };
106 
107 int board_usb_init(int index, enum usb_init_type init)
108 {
109 	int node;
110 	const char *mode;
111 	bool matched = false;
112 	const void *blob = gd->fdt_blob;
113 
114 	/* find the usb_otg node */
115 	node = fdt_node_offset_by_compatible(blob, -1,
116 					"rockchip,rk3288-usb");
117 
118 	while (node > 0) {
119 		mode = fdt_getprop(blob, node, "dr_mode", NULL);
120 		if (mode && strcmp(mode, "otg") == 0) {
121 			matched = true;
122 			break;
123 		}
124 
125 		node = fdt_node_offset_by_compatible(blob, node,
126 					"rockchip,rk3288-usb");
127 	}
128 	if (!matched) {
129 		debug("Not found usb_otg device\n");
130 		return -ENODEV;
131 	}
132 	rk322x_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
133 
134 	return dwc2_udc_probe(&rk322x_otg_data);
135 }
136 
137 int board_usb_cleanup(int index, enum usb_init_type init)
138 {
139 	return 0;
140 }
141 #endif
142 
143 #if defined(CONFIG_USB_FUNCTION_FASTBOOT)
144 int fb_set_reboot_flag(void)
145 {
146 	struct rk322x_grf *grf;
147 
148 	printf("Setting reboot to fastboot flag ...\n");
149 	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
150 	/* Set boot mode to fastboot */
151 	writel(BOOT_FASTBOOT, &grf->os_reg[0]);
152 
153 	return 0;
154 }
155 #endif
156