1 /* 2 * (C) Copyright 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <asm/io.h> 8 #include <asm/types.h> 9 #include <asm/arch/cru_rk3036.h> 10 #include <asm/arch/grf_rk3036.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/sdram_rk3036.h> 13 #include <asm/arch/timer.h> 14 #include <asm/arch/uart.h> 15 16 /* 17 * we can not fit the code to access the device tree in SPL 18 * (due to 4K SRAM size limits), so these are hard-coded 19 */ 20 #define CRU_BASE 0x20000000 21 #define GRF_BASE 0x20008000 22 #define DDR_PHY_BASE 0x2000a000 23 #define DDR_PCTL_BASE 0x20004000 24 #define CPU_AXI_BUS_BASE 0x10128000 25 26 struct rk3036_sdram_priv { 27 struct rk3036_cru *cru; 28 struct rk3036_grf *grf; 29 struct rk3036_ddr_phy *phy; 30 struct rk3036_ddr_pctl *pctl; 31 struct rk3036_service_sys *axi_bus; 32 33 /* ddr die config */ 34 struct rk3036_ddr_config ddr_config; 35 }; 36 37 /* 38 * use integer mode, dpll output 792MHz and ddr get 396MHz 39 * refdiv, fbdiv, postdiv1, postdiv2 40 */ 41 const struct pll_div dpll_init_cfg = {1, 66, 2, 1}; 42 43 /* 396Mhz ddr timing */ 44 const struct rk3036_ddr_timing ddr_timing = {0x18c, 45 {0x18c, 0xc8, 0x1f4, 0x27, 0x4e, 46 0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04, 47 0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03, 48 0x0c, 0x28, 0x100, 0x0, 0x04, 0x0}, 49 {{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60}, 50 {0x24717315} }; 51 52 /* 53 * [7:6] bank(n:n bit bank) 54 * [5:4] row(13+n) 55 * [3] cs(0:1 cs, 1:2 cs) 56 * [2:1] bank(n:n bit bank) 57 * [0] col(10+n) 58 */ 59 const char ddr_cfg_2_rbc[] = { 60 ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1), 61 ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0), 62 ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0), 63 ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0), 64 ((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1), 65 ((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1), 66 ((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1), 67 ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0), 68 ((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1), 69 ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0), 70 ((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1), 71 ((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0), 72 ((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1), 73 ((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0), 74 }; 75 76 /* DDRPHY REG */ 77 enum { 78 /* DDRPHY_REG1 */ 79 SOFT_RESET_MASK = 3, 80 SOFT_RESET_SHIFT = 2, 81 82 /* DDRPHY_REG2 */ 83 MEMORY_SELECT_DDR3 = 0 << 6, 84 DQS_SQU_CAL_NORMAL_MODE = 0 << 1, 85 DQS_SQU_CAL_START = 1 << 0, 86 DQS_SQU_NO_CAL = 0 << 0, 87 88 /* DDRPHY_REG2A */ 89 CMD_DLL_BYPASS = 1 << 4, 90 CMD_DLL_BYPASS_DISABLE = 0 << 4, 91 HIGH_8BIT_DLL_BYPASS = 1 << 3, 92 HIGH_8BIT_DLL_BYPASS_DISABLE = 0 << 3, 93 LOW_8BIT_DLL_BYPASS = 1 << 2, 94 LOW_8BIT_DLL_BYPASS_DISABLE = 0 << 2, 95 96 /* DDRPHY_REG19 */ 97 CMD_FEEDBACK_ENABLE = 1 << 5, 98 CMD_SLAVE_DLL_INVERSE_MODE = 1 << 4, 99 CMD_SLAVE_DLL_NO_INVERSE_MODE = 0 << 4, 100 CMD_SLAVE_DLL_ENALBE = 1 << 3, 101 CMD_TX_SLAVE_DLL_DELAY_MASK = 7, 102 CMD_TX_SLAVE_DLL_DELAY_SHIFT = 0, 103 104 /* DDRPHY_REG6 */ 105 LEFT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, 106 LEFT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, 107 LEFT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, 108 LEFT_CHN_TX_DQ_DLL_DELAY_MASK = 7, 109 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, 110 111 /* DDRPHY_REG8 */ 112 LEFT_CHN_RX_DQS_DELAY_TAP_MASK = 3, 113 LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, 114 115 /* DDRPHY_REG9 */ 116 RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 = 1 << 4, 117 RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 = 0 << 4, 118 RIGHT_CHN_TX_DQ_DLL_ENABLE = 1 << 3, 119 RIGHT_CHN_TX_DQ_DLL_DELAY_MASK = 7, 120 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT = 0, 121 122 /* DDRPHY_REG11 */ 123 RIGHT_CHN_RX_DQS_DELAY_TAP_MASK = 3, 124 RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT = 0, 125 126 /* DDRPHY_REG62 */ 127 CAL_DONE_MASK = 3, 128 HIGH_8BIT_CAL_DONE = 1 << 1, 129 LOW_8BIT_CAL_DONE = 1 << 0, 130 }; 131 132 /* PTCL */ 133 enum { 134 /* PCTL_DFISTCFG0 */ 135 DFI_INIT_START = 1 << 0, 136 DFI_DATA_BYTE_DISABLE_EN = 1 << 2, 137 138 /* PCTL_DFISTCFG1 */ 139 DFI_DRAM_CLK_SR_EN = 1 << 0, 140 DFI_DRAM_CLK_DPD_EN = 1 << 1, 141 142 /* PCTL_DFISTCFG2 */ 143 DFI_PARITY_INTR_EN = 1 << 0, 144 DFI_PARITY_EN = 1 << 1, 145 146 /* PCTL_DFILPCFG0 */ 147 TLP_RESP_TIME_SHIFT = 16, 148 LP_SR_EN = 1 << 8, 149 LP_PD_EN = 1 << 0, 150 151 /* PCTL_DFIODTCFG */ 152 RANK0_ODT_WRITE_SEL = 1 << 3, 153 RANK1_ODT_WRITE_SEL = 1 << 11, 154 155 /* PCTL_DFIODTCFG1 */ 156 ODT_LEN_BL8_W_SHIFT = 16, 157 158 /* PCTL_MCFG */ 159 TFAW_CFG_MASK = 3, 160 TFAW_CFG_SHIFT = 18, 161 PD_EXIT_SLOW_MODE = 0 << 17, 162 PD_ACTIVE_POWER_DOWN = 1 << 16, 163 PD_IDLE_MASK = 0xff, 164 PD_IDLE_SHIFT = 8, 165 MEM_BL4 = 0 << 0, 166 MEM_BL8 = 1 << 0, 167 168 /* PCTL_MCFG1 */ 169 HW_EXIT_IDLE_EN_MASK = 1, 170 HW_EXIT_IDLE_EN_SHIFT = 31, 171 SR_IDLE_MASK = 0x1ff, 172 SR_IDLE_SHIFT = 0, 173 174 /* PCTL_SCFG */ 175 HW_LOW_POWER_EN = 1 << 0, 176 177 /* PCTL_POWCTL */ 178 POWER_UP_START = 1 << 0, 179 180 /* PCTL_POWSTAT */ 181 POWER_UP_DONE = 1 << 0, 182 183 /* PCTL_MCMD */ 184 START_CMD = 1 << 31, 185 BANK_ADDR_MASK = 7, 186 BANK_ADDR_SHIFT = 17, 187 CMD_ADDR_MASK = 0x1fff, 188 CMD_ADDR_SHIFT = 4, 189 DESELECT_CMD = 0, 190 PREA_CMD, 191 REF_CMD, 192 MRS_CMD, 193 ZQCS_CMD, 194 ZQCL_CMD, 195 RSTL_CMD, 196 MRR_CMD = 8, 197 198 /* PCTL_STAT */ 199 INIT_MEM = 0, 200 CONFIG, 201 CONFIG_REQ, 202 ACCESS, 203 ACCESS_REQ, 204 LOW_POWER, 205 LOW_POWER_ENTRY_REQ, 206 LOW_POWER_EXIT_REQ, 207 PCTL_STAT_MASK = 7, 208 209 /* PCTL_SCTL */ 210 INIT_STATE = 0, 211 CFG_STATE = 1, 212 GO_STATE = 2, 213 SLEEP_STATE = 3, 214 WAKEUP_STATE = 4, 215 }; 216 217 /* GRF_SOC_CON2 */ 218 #define MSCH4_MAINDDR3 (1 << 7) 219 #define PHY_DRV_ODT_SET(n) ((n << 4) | n) 220 #define DDR3_DLL_RESET (1 << 8) 221 222 /* CK pull up/down driver strength control */ 223 enum { 224 PHY_RON_DISABLE = 0, 225 PHY_RON_309OHM = 1, 226 PHY_RON_155OHM, 227 PHY_RON_103OHM = 3, 228 PHY_RON_63OHM = 5, 229 PHY_RON_45OHM = 7, 230 PHY_RON_77OHM, 231 PHY_RON_62OHM, 232 PHY_RON_52OHM, 233 PHY_RON_44OHM, 234 PHY_RON_39OHM, 235 PHY_RON_34OHM, 236 PHY_RON_31OHM, 237 PHY_RON_28OHM, 238 }; 239 240 /* DQ pull up/down control */ 241 enum { 242 PHY_RTT_DISABLE = 0, 243 PHY_RTT_861OHM = 1, 244 PHY_RTT_431OHM, 245 PHY_RTT_287OHM, 246 PHY_RTT_216OHM, 247 PHY_RTT_172OHM, 248 PHY_RTT_145OHM, 249 PHY_RTT_124OHM, 250 PHY_RTT_215OHM, 251 PHY_RTT_144OHM = 0xa, 252 PHY_RTT_123OHM, 253 PHY_RTT_108OHM, 254 PHY_RTT_96OHM, 255 PHY_RTT_86OHM, 256 PHY_RTT_78OHM, 257 }; 258 259 /* DQS squelch DLL delay */ 260 enum { 261 DQS_DLL_NO_DELAY = 0, 262 DQS_DLL_22P5_DELAY, 263 DQS_DLL_45_DELAY, 264 DQS_DLL_67P5_DELAY, 265 DQS_DLL_90_DELAY, 266 DQS_DLL_112P5_DELAY, 267 DQS_DLL_135_DELAY, 268 DQS_DLL_157P5_DELAY, 269 }; 270 271 /* GRF_OS_REG1 */ 272 enum { 273 /* 274 * 000: lpddr 275 * 001: ddr 276 * 010: ddr2 277 * 011: ddr3 278 * 100: lpddr2-s2 279 * 101: lpddr2-s4 280 * 110: lpddr3 281 */ 282 DDR_TYPE_MASK = 7, 283 DDR_TYPE_SHIFT = 13, 284 285 /* 0: 1 chn, 1: 2 chn */ 286 DDR_CHN_CNT_SHIFT = 12, 287 288 /* 0: 1 rank, 1: 2 rank */ 289 DDR_RANK_CNT_MASK = 1, 290 DDR_RANK_CNT_SHIFT = 11, 291 292 /* 293 * 00: 9col 294 * 01: 10col 295 * 10: 11col 296 * 11: 12col 297 */ 298 DDR_COL_MASK = 3, 299 DDR_COL_SHIFT = 9, 300 301 /* 0: 8 bank, 1: 4 bank*/ 302 DDR_BANK_MASK = 1, 303 DDR_BANK_SHIFT = 8, 304 305 /* 306 * 00: 13 row 307 * 01: 14 row 308 * 10: 15 row 309 * 11: 16 row 310 */ 311 DDR_CS0_ROW_MASK = 3, 312 DDR_CS0_ROW_SHIFT = 6, 313 DDR_CS1_ROW_MASK = 3, 314 DDR_CS1_ROW_SHIFT = 4, 315 316 /* 317 * 00: 32 bit 318 * 01: 16 bit 319 * 10: 8 bit 320 * rk3036 only support 16bit 321 */ 322 DDR_BW_MASK = 3, 323 DDR_BW_SHIFT = 2, 324 DDR_DIE_BW_MASK = 3, 325 DDR_DIE_BW_SHIFT = 0, 326 }; 327 328 static void rkdclk_init(struct rk3036_sdram_priv *priv) 329 { 330 struct rk3036_pll *pll = &priv->cru->pll[1]; 331 332 /* pll enter slow-mode */ 333 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, 334 DPLL_MODE_SLOW << DPLL_MODE_SHIFT); 335 336 /* use integer mode */ 337 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); 338 339 rk_clrsetreg(&pll->con0, 340 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK, 341 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | 342 dpll_init_cfg.fbdiv); 343 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, 344 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | 345 dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT)); 346 347 /* waiting for pll lock */ 348 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) 349 rockchip_udelay(1); 350 351 /* PLL enter normal-mode */ 352 rk_clrsetreg(&priv->cru->cru_mode_con, DPLL_MODE_MASK, 353 DPLL_MODE_NORM << DPLL_MODE_SHIFT); 354 } 355 356 static void copy_to_reg(u32 *dest, const u32 *src, u32 n) 357 { 358 int i; 359 360 for (i = 0; i < n / sizeof(u32); i++) { 361 writel(*src, dest); 362 src++; 363 dest++; 364 } 365 } 366 367 void phy_pctrl_reset(struct rk3036_sdram_priv *priv) 368 { 369 struct rk3036_ddr_phy *ddr_phy = priv->phy; 370 371 rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 372 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 373 1 << DDRPHY_SRST_SHIFT, 374 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 375 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); 376 377 rockchip_udelay(10); 378 379 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 380 1 << DDRPHY_SRST_SHIFT); 381 rockchip_udelay(10); 382 383 rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 384 1 << DDRCTRL_SRST_SHIFT); 385 rockchip_udelay(10); 386 387 clrsetbits_le32(&ddr_phy->ddrphy_reg1, 388 SOFT_RESET_MASK << SOFT_RESET_SHIFT, 389 0 << SOFT_RESET_SHIFT); 390 rockchip_udelay(10); 391 clrsetbits_le32(&ddr_phy->ddrphy_reg1, 392 SOFT_RESET_MASK << SOFT_RESET_SHIFT, 393 3 << SOFT_RESET_SHIFT); 394 395 rockchip_udelay(1); 396 } 397 398 void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq) 399 { 400 struct rk3036_ddr_phy *ddr_phy = priv->phy; 401 402 if (freq < ddr_timing.freq) { 403 writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS | 404 LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a); 405 406 writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 | 407 LEFT_CHN_TX_DQ_DLL_ENABLE | 408 (0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << 409 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6); 410 411 writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 | 412 RIGHT_CHN_TX_DQ_DLL_ENABLE | 413 (0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << 414 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, 415 &ddr_phy->ddrphy_reg9); 416 } else { 417 writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE | 418 LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a); 419 420 writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 | 421 LEFT_CHN_TX_DQ_DLL_ENABLE | 422 (4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) << 423 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, 424 &ddr_phy->ddrphy_reg6); 425 426 writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 | 427 RIGHT_CHN_TX_DQ_DLL_ENABLE | 428 (4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) << 429 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT, 430 &ddr_phy->ddrphy_reg9); 431 } 432 433 writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE | 434 (0 & CMD_TX_SLAVE_DLL_DELAY_MASK) << 435 CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19); 436 437 /* 45 degree delay */ 438 writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) << 439 LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8); 440 writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) << 441 RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11); 442 } 443 444 static void send_command(struct rk3036_ddr_pctl *pctl, 445 u32 rank, u32 cmd, u32 arg) 446 { 447 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); 448 rockchip_udelay(1); 449 while (readl(&pctl->mcmd) & START_CMD) 450 ; 451 } 452 453 static void memory_init(struct rk3036_sdram_priv *priv) 454 { 455 struct rk3036_ddr_pctl *pctl = priv->pctl; 456 457 send_command(pctl, 3, DESELECT_CMD, 0); 458 rockchip_udelay(1); 459 send_command(pctl, 3, PREA_CMD, 0); 460 send_command(pctl, 3, MRS_CMD, 461 (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << 463 CMD_ADDR_SHIFT); 464 465 send_command(pctl, 3, MRS_CMD, 466 (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << 468 CMD_ADDR_SHIFT); 469 470 send_command(pctl, 3, MRS_CMD, 471 (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << 473 CMD_ADDR_SHIFT); 474 475 send_command(pctl, 3, MRS_CMD, 476 (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | 477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << 478 CMD_ADDR_SHIFT | DDR3_DLL_RESET); 479 480 send_command(pctl, 3, ZQCL_CMD, 0); 481 } 482 483 static void data_training(struct rk3036_sdram_priv *priv) 484 { 485 struct rk3036_ddr_phy *ddr_phy = priv->phy; 486 struct rk3036_ddr_pctl *pctl = priv->pctl; 487 u32 value; 488 489 /* disable auto refresh */ 490 value = readl(&pctl->trefi), 491 writel(0, &pctl->trefi); 492 493 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, 494 DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START); 495 496 rockchip_udelay(1); 497 while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) != 498 (HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) { 499 ; 500 } 501 502 clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03, 503 DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL); 504 505 /* 506 * since data training will take about 20us, so send some auto 507 * refresh(about 7.8us) to complement the lost time 508 */ 509 send_command(pctl, 3, REF_CMD, 0); 510 send_command(pctl, 3, REF_CMD, 0); 511 send_command(pctl, 3, REF_CMD, 0); 512 513 writel(value, &pctl->trefi); 514 } 515 516 static void move_to_config_state(struct rk3036_sdram_priv *priv) 517 { 518 unsigned int state; 519 struct rk3036_ddr_pctl *pctl = priv->pctl; 520 521 while (1) { 522 state = readl(&pctl->stat) & PCTL_STAT_MASK; 523 switch (state) { 524 case LOW_POWER: 525 writel(WAKEUP_STATE, &pctl->sctl); 526 while ((readl(&pctl->stat) & PCTL_STAT_MASK) 527 != ACCESS) 528 ; 529 /* 530 * If at low power state, need wakeup first, and then 531 * enter the config, so fallthrough 532 */ 533 case ACCESS: 534 /* fallthrough */ 535 case INIT_MEM: 536 writel(CFG_STATE, &pctl->sctl); 537 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) 538 ; 539 break; 540 case CONFIG: 541 return; 542 default: 543 break; 544 } 545 } 546 } 547 548 static void move_to_access_state(struct rk3036_sdram_priv *priv) 549 { 550 unsigned int state; 551 struct rk3036_ddr_pctl *pctl = priv->pctl; 552 553 while (1) { 554 state = readl(&pctl->stat) & PCTL_STAT_MASK; 555 switch (state) { 556 case LOW_POWER: 557 writel(WAKEUP_STATE, &pctl->sctl); 558 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) 559 ; 560 break; 561 case INIT_MEM: 562 writel(CFG_STATE, &pctl->sctl); 563 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG) 564 ; 565 /* fallthrough */ 566 case CONFIG: 567 writel(GO_STATE, &pctl->sctl); 568 while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS) 569 ; 570 break; 571 case ACCESS: 572 return; 573 default: 574 break; 575 } 576 } 577 } 578 579 static void pctl_cfg(struct rk3036_sdram_priv *priv) 580 { 581 struct rk3036_ddr_pctl *pctl = priv->pctl; 582 u32 burst_len; 583 u32 reg; 584 585 writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0); 586 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1); 587 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); 588 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, 589 &pctl->dfilpcfg0); 590 591 writel(1, &pctl->dfitphyupdtype0); 592 writel(0x0d, &pctl->dfitphyrdlat); 593 594 /* cs0 and cs1 write odt enable */ 595 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), 596 &pctl->dfiodtcfg); 597 598 /* odt write length */ 599 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); 600 601 /* phyupd and ctrlupd disabled */ 602 writel(0, &pctl->dfiupdcfg); 603 604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) 605 burst_len = MEM_BL4; 606 else 607 burst_len = MEM_BL8; 608 609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, 610 sizeof(struct rk3036_pctl_timing)); 611 reg = readl(&pctl->tcl); 612 writel(reg - 3, &pctl->dfitrddataen); 613 reg = readl(&pctl->tcwl); 614 writel(reg - 1, &pctl->dfitphywrlat); 615 616 writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT | 617 PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN | 618 (0 & PD_IDLE_MASK) << PD_IDLE_SHIFT, 619 &pctl->mcfg); 620 621 writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2); 622 setbits_le32(&pctl->scfg, HW_LOW_POWER_EN); 623 } 624 625 static void phy_cfg(struct rk3036_sdram_priv *priv) 626 { 627 struct rk3036_ddr_phy *ddr_phy = priv->phy; 628 struct rk3036_service_sys *axi_bus = priv->axi_bus; 629 630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); 631 writel(0x3f, &axi_bus->readlatency); 632 633 writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE, 634 &ddr_phy->ddrphy_reg2); 635 636 clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl); 637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); 638 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16); 639 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22); 640 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25); 641 writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26); 642 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27); 643 writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28); 644 } 645 646 void dram_cfg_rbc(struct rk3036_sdram_priv *priv) 647 { 648 char noc_config; 649 int i = 0; 650 struct rk3036_ddr_config config = priv->ddr_config; 651 struct rk3036_service_sys *axi_bus = priv->axi_bus; 652 653 move_to_config_state(priv); 654 655 /* 2bit in BIT1, 2 */ 656 if (config.rank == 2) { 657 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | 658 1 << 3 | (config.col - 10); 659 if (noc_config == ddr_cfg_2_rbc[9]) { 660 i = 9; 661 goto finish; 662 } else if (noc_config == ddr_cfg_2_rbc[10]) { 663 i = 10; 664 goto finish; 665 } 666 } 667 668 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | 669 (config.col - 10); 670 671 for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) { 672 if (noc_config == ddr_cfg_2_rbc[i]) 673 goto finish; 674 } 675 676 /* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */ 677 noc_config = 1 << 6 | (config.cs0_row - 13) << 4 | 678 2 << 1 | (config.col - 10); 679 if (noc_config == ddr_cfg_2_rbc[11]) { 680 i = 11; 681 goto finish; 682 } 683 684 /* bank: 2bit in BIT6,7 */ 685 noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 | 686 (config.col - 10); 687 688 if (noc_config == ddr_cfg_2_rbc[0]) 689 i = 0; 690 else if (noc_config == ddr_cfg_2_rbc[12]) 691 i = 12; 692 else if (noc_config == ddr_cfg_2_rbc[13]) 693 i = 13; 694 finish: 695 writel(i, &axi_bus->ddrconf); 696 move_to_access_state(priv); 697 } 698 699 static void sdram_all_config(struct rk3036_sdram_priv *priv) 700 { 701 u32 os_reg = 0; 702 u32 cs1_row = 0; 703 struct rk3036_ddr_config config = priv->ddr_config; 704 705 if (config.rank > 1) 706 cs1_row = config.cs1_row - 13; 707 708 os_reg = config.ddr_type << DDR_TYPE_SHIFT | 709 0 << DDR_CHN_CNT_SHIFT | 710 (config.rank - 1) << DDR_RANK_CNT_SHIFT | 711 (config.col - 9) << DDR_COL_SHIFT | 712 (config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT | 713 (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT | 714 cs1_row << DDR_CS1_ROW_SHIFT | 715 1 << DDR_BW_SHIFT | 716 (2 >> config.bw) << DDR_DIE_BW_SHIFT; 717 writel(os_reg, &priv->grf->os_reg[1]); 718 } 719 720 size_t sdram_size(void) 721 { 722 u32 size, os_reg, cs0_row, cs1_row, col, bank, rank; 723 struct rk3036_grf *grf = (void *)GRF_BASE; 724 725 os_reg = readl(&grf->os_reg[1]); 726 727 cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK); 728 cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK); 729 col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK); 730 bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK); 731 rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK); 732 733 /* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */ 734 size = 1 << (cs0_row + col + bank + 1); 735 736 if (rank > 1) 737 size += size >> (cs0_row - cs1_row); 738 739 return size; 740 } 741 742 void sdram_init(void) 743 { 744 struct rk3036_sdram_priv sdram_priv; 745 746 sdram_priv.cru = (void *)CRU_BASE; 747 sdram_priv.grf = (void *)GRF_BASE; 748 sdram_priv.phy = (void *)DDR_PHY_BASE; 749 sdram_priv.pctl = (void *)DDR_PCTL_BASE; 750 sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE; 751 752 get_ddr_config(&sdram_priv.ddr_config); 753 sdram_all_config(&sdram_priv); 754 rkdclk_init(&sdram_priv); 755 phy_pctrl_reset(&sdram_priv); 756 phy_dll_bypass_set(&sdram_priv, ddr_timing.freq); 757 pctl_cfg(&sdram_priv); 758 phy_cfg(&sdram_priv); 759 writel(POWER_UP_START, &sdram_priv.pctl->powctl); 760 while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE)) 761 ; 762 memory_init(&sdram_priv); 763 move_to_config_state(&sdram_priv); 764 data_training(&sdram_priv); 765 move_to_access_state(&sdram_priv); 766 dram_cfg_rbc(&sdram_priv); 767 } 768