1 /*
2  * (C) Copyright 2015 Google, Inc
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6 #include <common.h>
7 #include <asm/io.h>
8 #include <asm/types.h>
9 #include <asm/arch/cru_rk3036.h>
10 #include <asm/arch/grf_rk3036.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/sdram_rk3036.h>
13 #include <asm/arch/timer.h>
14 #include <asm/arch/uart.h>
15 
16 /*
17  * we can not fit the code to access the device tree in SPL
18  * (due to 4K SRAM size limits), so these are hard-coded
19  */
20 #define CRU_BASE	0x20000000
21 #define GRF_BASE	0x20008000
22 #define DDR_PHY_BASE	0x2000a000
23 #define DDR_PCTL_BASE	0x20004000
24 #define CPU_AXI_BUS_BASE	0x10128000
25 
26 struct rk3036_sdram_priv {
27 	struct rk3036_cru *cru;
28 	struct rk3036_grf *grf;
29 	struct rk3036_ddr_phy *phy;
30 	struct rk3036_ddr_pctl *pctl;
31 	struct rk3036_service_sys *axi_bus;
32 
33 	/* ddr die config */
34 	struct rk3036_ddr_config ddr_config;
35 };
36 
37 /* use integer mode, 396MHz dpll setting
38  * refdiv, fbdiv, postdiv1, postdiv2
39  */
40 const struct pll_div dpll_init_cfg = {1, 66, 4, 1};
41 
42 /* 396Mhz ddr timing */
43 const struct rk3036_ddr_timing ddr_timing = {0x18c,
44 	{0x18c, 0xc8, 0x1f4, 0x27, 0x4e,
45 	0x4, 0x8b, 0x06, 0x03, 0x0, 0x06, 0x05, 0x0f, 0x15, 0x06, 0x04, 0x04,
46 	0x06, 0x04, 0x200, 0x03, 0x0a, 0x40, 0x2710, 0x01, 0x05, 0x05, 0x03,
47 	0x0c, 0x28, 0x100, 0x0, 0x04, 0x0},
48 	{{0x420, 0x42, 0x0, 0x0}, 0x01, 0x60},
49 	{0x24717315} };
50 
51 /*
52  * [7:6]  bank(n:n bit bank)
53  * [5:4]  row(13+n)
54  * [3]    cs(0:1 cs, 1:2 cs)
55  * [2:1]  bank(n:n bit bank)
56  * [0]    col(10+n)
57  */
58 const char ddr_cfg_2_rbc[] = {
59 	((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 1),
60 	((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 0),
61 	((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 0),
62 	((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 0),
63 	((0 << 6) | (1 << 4) | (0 << 3) | (3 << 1) | 1),
64 	((0 << 6) | (2 << 4) | (0 << 3) | (3 << 1) | 1),
65 	((0 << 6) | (3 << 4) | (0 << 3) | (3 << 1) | 1),
66 	((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 0),
67 	((0 << 6) | (0 << 4) | (0 << 3) | (3 << 1) | 1),
68 	((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 0),
69 	((0 << 6) | (3 << 4) | (1 << 3) | (3 << 1) | 1),
70 	((1 << 6) | (2 << 4) | (0 << 3) | (2 << 1) | 0),
71 	((3 << 6) | (2 << 4) | (0 << 3) | (0 << 1) | 1),
72 	((3 << 6) | (3 << 4) | (0 << 3) | (0 << 1) | 0),
73 };
74 
75 /* DDRPHY REG */
76 enum {
77 	/* DDRPHY_REG1 */
78 	SOFT_RESET_MASK				= 3,
79 	SOFT_RESET_SHIFT			= 2,
80 
81 	/* DDRPHY_REG2 */
82 	MEMORY_SELECT_DDR3			= 0 << 6,
83 	DQS_SQU_CAL_NORMAL_MODE			= 0 << 1,
84 	DQS_SQU_CAL_START			= 1 << 0,
85 	DQS_SQU_NO_CAL				= 0 << 0,
86 
87 	/* DDRPHY_REG2A */
88 	CMD_DLL_BYPASS				= 1 << 4,
89 	CMD_DLL_BYPASS_DISABLE			= 0 << 4,
90 	HIGH_8BIT_DLL_BYPASS			= 1 << 3,
91 	HIGH_8BIT_DLL_BYPASS_DISABLE		= 0 << 3,
92 	LOW_8BIT_DLL_BYPASS			= 1 << 2,
93 	LOW_8BIT_DLL_BYPASS_DISABLE		= 0 << 2,
94 
95 	/* DDRPHY_REG19 */
96 	CMD_FEEDBACK_ENABLE			= 1 << 5,
97 	CMD_SLAVE_DLL_INVERSE_MODE		= 1 << 4,
98 	CMD_SLAVE_DLL_NO_INVERSE_MODE		= 0 << 4,
99 	CMD_SLAVE_DLL_ENALBE			= 1 << 3,
100 	CMD_TX_SLAVE_DLL_DELAY_MASK		= 7,
101 	CMD_TX_SLAVE_DLL_DELAY_SHIFT		= 0,
102 
103 	/* DDRPHY_REG6 */
104 	LEFT_CHN_TX_DQ_PHASE_BYPASS_90		= 1 << 4,
105 	LEFT_CHN_TX_DQ_PHASE_BYPASS_0		= 0 << 4,
106 	LEFT_CHN_TX_DQ_DLL_ENABLE		= 1 << 3,
107 	LEFT_CHN_TX_DQ_DLL_DELAY_MASK		= 7,
108 	LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT		= 0,
109 
110 	/* DDRPHY_REG8 */
111 	LEFT_CHN_RX_DQS_DELAY_TAP_MASK		= 3,
112 	LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT		= 0,
113 
114 	/* DDRPHY_REG9 */
115 	RIGHT_CHN_TX_DQ_PHASE_BYPASS_90		= 1 << 4,
116 	RIGHT_CHN_TX_DQ_PHASE_BYPASS_0		= 0 << 4,
117 	RIGHT_CHN_TX_DQ_DLL_ENABLE		= 1 << 3,
118 	RIGHT_CHN_TX_DQ_DLL_DELAY_MASK		= 7,
119 	RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT		= 0,
120 
121 	/* DDRPHY_REG11 */
122 	RIGHT_CHN_RX_DQS_DELAY_TAP_MASK		= 3,
123 	RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT	= 0,
124 
125 	/* DDRPHY_REG62 */
126 	CAL_DONE_MASK				= 3,
127 	HIGH_8BIT_CAL_DONE			= 1 << 1,
128 	LOW_8BIT_CAL_DONE			= 1 << 0,
129 };
130 
131 /* PTCL */
132 enum {
133 	/* PCTL_DFISTCFG0 */
134 	DFI_INIT_START			= 1 << 0,
135 	DFI_DATA_BYTE_DISABLE_EN	= 1 << 2,
136 
137 	/* PCTL_DFISTCFG1 */
138 	DFI_DRAM_CLK_SR_EN		= 1 << 0,
139 	DFI_DRAM_CLK_DPD_EN		= 1 << 1,
140 
141 	/* PCTL_DFISTCFG2 */
142 	DFI_PARITY_INTR_EN		= 1 << 0,
143 	DFI_PARITY_EN			= 1 << 1,
144 
145 	/* PCTL_DFILPCFG0 */
146 	TLP_RESP_TIME_SHIFT		= 16,
147 	LP_SR_EN			= 1 << 8,
148 	LP_PD_EN			= 1 << 0,
149 
150 	/* PCTL_DFIODTCFG */
151 	RANK0_ODT_WRITE_SEL		= 1 << 3,
152 	RANK1_ODT_WRITE_SEL		= 1 << 11,
153 
154 	/* PCTL_DFIODTCFG1 */
155 	ODT_LEN_BL8_W_SHIFT		= 16,
156 
157 	/* PCTL_MCFG */
158 	TFAW_CFG_MASK			= 3,
159 	TFAW_CFG_SHIFT			= 18,
160 	PD_EXIT_SLOW_MODE		= 0 << 17,
161 	PD_ACTIVE_POWER_DOWN		= 1 << 16,
162 	PD_IDLE_MASK			= 0xff,
163 	PD_IDLE_SHIFT			= 8,
164 	MEM_BL4				= 0 << 0,
165 	MEM_BL8				= 1 << 0,
166 
167 	/* PCTL_MCFG1 */
168 	HW_EXIT_IDLE_EN_MASK		= 1,
169 	HW_EXIT_IDLE_EN_SHIFT		= 31,
170 	SR_IDLE_MASK			= 0x1ff,
171 	SR_IDLE_SHIFT			= 0,
172 
173 	/* PCTL_SCFG */
174 	HW_LOW_POWER_EN			= 1 << 0,
175 
176 	/* PCTL_POWCTL */
177 	POWER_UP_START			= 1 << 0,
178 
179 	/* PCTL_POWSTAT */
180 	POWER_UP_DONE			= 1 << 0,
181 
182 	/* PCTL_MCMD */
183 	START_CMD			= 1 << 31,
184 	BANK_ADDR_MASK			= 7,
185 	BANK_ADDR_SHIFT			= 17,
186 	CMD_ADDR_MASK			= 0x1fff,
187 	CMD_ADDR_SHIFT			= 4,
188 	DESELECT_CMD			= 0,
189 	PREA_CMD,
190 	REF_CMD,
191 	MRS_CMD,
192 	ZQCS_CMD,
193 	ZQCL_CMD,
194 	RSTL_CMD,
195 	MRR_CMD				= 8,
196 
197 	/* PCTL_STAT */
198 	INIT_MEM			= 0,
199 	CONFIG,
200 	CONFIG_REQ,
201 	ACCESS,
202 	ACCESS_REQ,
203 	LOW_POWER,
204 	LOW_POWER_ENTRY_REQ,
205 	LOW_POWER_EXIT_REQ,
206 	PCTL_STAT_MASK			= 7,
207 
208 	/* PCTL_SCTL */
209 	INIT_STATE			= 0,
210 	CFG_STATE			= 1,
211 	GO_STATE			= 2,
212 	SLEEP_STATE			= 3,
213 	WAKEUP_STATE			= 4,
214 };
215 
216 /* GRF_SOC_CON2 */
217 #define	MSCH4_MAINDDR3		(1 << 7)
218 #define PHY_DRV_ODT_SET(n)	((n << 4) | n)
219 #define DDR3_DLL_RESET		(1 << 8)
220 
221 /* CK pull up/down driver strength control */
222 enum {
223 	PHY_RON_DISABLE		= 0,
224 	PHY_RON_309OHM		= 1,
225 	PHY_RON_155OHM,
226 	PHY_RON_103OHM		= 3,
227 	PHY_RON_63OHM		= 5,
228 	PHY_RON_45OHM		= 7,
229 	PHY_RON_77OHM,
230 	PHY_RON_62OHM,
231 	PHY_RON_52OHM,
232 	PHY_RON_44OHM,
233 	PHY_RON_39OHM,
234 	PHY_RON_34OHM,
235 	PHY_RON_31OHM,
236 	PHY_RON_28OHM,
237 };
238 
239 /* DQ pull up/down control */
240 enum {
241 	PHY_RTT_DISABLE		= 0,
242 	PHY_RTT_861OHM		= 1,
243 	PHY_RTT_431OHM,
244 	PHY_RTT_287OHM,
245 	PHY_RTT_216OHM,
246 	PHY_RTT_172OHM,
247 	PHY_RTT_145OHM,
248 	PHY_RTT_124OHM,
249 	PHY_RTT_215OHM,
250 	PHY_RTT_144OHM		= 0xa,
251 	PHY_RTT_123OHM,
252 	PHY_RTT_108OHM,
253 	PHY_RTT_96OHM,
254 	PHY_RTT_86OHM,
255 	PHY_RTT_78OHM,
256 };
257 
258 /* DQS squelch DLL delay */
259 enum {
260 	DQS_DLL_NO_DELAY	= 0,
261 	DQS_DLL_22P5_DELAY,
262 	DQS_DLL_45_DELAY,
263 	DQS_DLL_67P5_DELAY,
264 	DQS_DLL_90_DELAY,
265 	DQS_DLL_112P5_DELAY,
266 	DQS_DLL_135_DELAY,
267 	DQS_DLL_157P5_DELAY,
268 };
269 
270 /* GRF_OS_REG1 */
271 enum {
272 	/*
273 	 * 000: lpddr
274 	 * 001: ddr
275 	 * 010: ddr2
276 	 * 011: ddr3
277 	 * 100: lpddr2-s2
278 	 * 101: lpddr2-s4
279 	 * 110: lpddr3
280 	 */
281 	DDR_TYPE_MASK		= 7,
282 	DDR_TYPE_SHIFT		= 13,
283 
284 	/* 0: 1 chn, 1: 2 chn */
285 	DDR_CHN_CNT_SHIFT	= 12,
286 
287 	/* 0: 1 rank, 1: 2 rank */
288 	DDR_RANK_CNT_MASK	= 1,
289 	DDR_RANK_CNT_SHIFT	= 11,
290 
291 	/*
292 	 * 00: 9col
293 	 * 01: 10col
294 	 * 10: 11col
295 	 * 11: 12col
296 	 */
297 	DDR_COL_MASK		= 3,
298 	DDR_COL_SHIFT		= 9,
299 
300 	/* 0: 8 bank, 1: 4 bank*/
301 	DDR_BANK_MASK		= 1,
302 	DDR_BANK_SHIFT		= 8,
303 
304 	/*
305 	 * 00: 13 row
306 	 * 01: 14 row
307 	 * 10: 15 row
308 	 * 11: 16 row
309 	 */
310 	DDR_CS0_ROW_MASK	= 3,
311 	DDR_CS0_ROW_SHIFT	= 6,
312 	DDR_CS1_ROW_MASK	= 3,
313 	DDR_CS1_ROW_SHIFT	= 4,
314 
315 	/*
316 	 * 00: 32 bit
317 	 * 01: 16 bit
318 	 * 10: 8 bit
319 	 * rk3036 only support 16bit
320 	 */
321 	DDR_BW_MASK		= 3,
322 	DDR_BW_SHIFT		= 2,
323 	DDR_DIE_BW_MASK		= 3,
324 	DDR_DIE_BW_SHIFT	= 0,
325 };
326 
327 static void rkdclk_init(struct rk3036_sdram_priv *priv)
328 {
329 	struct rk3036_pll *pll = &priv->cru->pll[1];
330 
331 	/* pll enter slow-mode */
332 	rk_clrsetreg(&priv->cru->cru_mode_con,
333 		     DPLL_MODE_MASK << DPLL_MODE_SHIFT,
334 		     DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
335 
336 	/* use integer mode */
337 	rk_clrreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
338 
339 	rk_clrsetreg(&pll->con0,
340 		     PLL_POSTDIV1_MASK << PLL_POSTDIV1_SHIFT | PLL_FBDIV_MASK,
341 		     (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) |
342 			dpll_init_cfg.fbdiv);
343 	rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK << PLL_POSTDIV2_SHIFT |
344 			PLL_REFDIV_MASK << PLL_REFDIV_SHIFT,
345 			(dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT |
346 			 dpll_init_cfg.refdiv << PLL_REFDIV_SHIFT));
347 
348 	/* waiting for pll lock */
349 	while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
350 		rockchip_udelay(1);
351 
352 	/* PLL enter normal-mode */
353 	rk_clrsetreg(&priv->cru->cru_mode_con,
354 		     DPLL_MODE_MASK << DPLL_MODE_SHIFT,
355 		     DPLL_MODE_NORM << DPLL_MODE_SHIFT);
356 }
357 
358 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
359 {
360 	int i;
361 
362 	for (i = 0; i < n / sizeof(u32); i++) {
363 		writel(*src, dest);
364 		src++;
365 		dest++;
366 	}
367 }
368 
369 void phy_pctrl_reset(struct rk3036_sdram_priv *priv)
370 {
371 	struct rk3036_ddr_phy *ddr_phy = priv->phy;
372 
373 	rk_clrsetreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
374 			1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT |
375 			1 << DDRPHY_SRST_SHIFT,
376 			1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT |
377 			1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT);
378 
379 	rockchip_udelay(10);
380 
381 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT |
382 						  1 << DDRPHY_SRST_SHIFT);
383 	rockchip_udelay(10);
384 
385 	rk_clrreg(&priv->cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT |
386 						  1 << DDRCTRL_SRST_SHIFT);
387 	rockchip_udelay(10);
388 
389 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
390 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
391 			0 << SOFT_RESET_SHIFT);
392 	rockchip_udelay(10);
393 	clrsetbits_le32(&ddr_phy->ddrphy_reg1,
394 			SOFT_RESET_MASK << SOFT_RESET_SHIFT,
395 			3 << SOFT_RESET_SHIFT);
396 
397 	rockchip_udelay(1);
398 }
399 
400 void phy_dll_bypass_set(struct rk3036_sdram_priv *priv, unsigned int freq)
401 {
402 	struct rk3036_ddr_phy *ddr_phy = priv->phy;
403 
404 	if (freq < ddr_timing.freq) {
405 		writel(CMD_DLL_BYPASS | HIGH_8BIT_DLL_BYPASS |
406 			LOW_8BIT_DLL_BYPASS, &ddr_phy->ddrphy_reg2a);
407 
408 		writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_90 |
409 			LEFT_CHN_TX_DQ_DLL_ENABLE |
410 			(0 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
411 			 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg6);
412 
413 		writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_90 |
414 			RIGHT_CHN_TX_DQ_DLL_ENABLE |
415 			(0 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
416 			 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
417 			&ddr_phy->ddrphy_reg9);
418 	} else {
419 		writel(CMD_DLL_BYPASS_DISABLE | HIGH_8BIT_DLL_BYPASS_DISABLE |
420 			LOW_8BIT_DLL_BYPASS_DISABLE, &ddr_phy->ddrphy_reg2a);
421 
422 		writel(LEFT_CHN_TX_DQ_PHASE_BYPASS_0 |
423 			LEFT_CHN_TX_DQ_DLL_ENABLE |
424 			(4 & LEFT_CHN_TX_DQ_DLL_DELAY_MASK) <<
425 			 LEFT_CHN_TX_DQ_DLL_DELAY_SHIFT,
426 			&ddr_phy->ddrphy_reg6);
427 
428 		writel(RIGHT_CHN_TX_DQ_PHASE_BYPASS_0 |
429 			RIGHT_CHN_TX_DQ_DLL_ENABLE |
430 			(4 & RIGHT_CHN_TX_DQ_DLL_DELAY_MASK) <<
431 			 RIGHT_CHN_TX_DQ_DLL_DELAY_SHIFT,
432 			&ddr_phy->ddrphy_reg9);
433 	}
434 
435 	writel(CMD_SLAVE_DLL_NO_INVERSE_MODE | CMD_SLAVE_DLL_ENALBE |
436 			(0 & CMD_TX_SLAVE_DLL_DELAY_MASK) <<
437 			CMD_TX_SLAVE_DLL_DELAY_SHIFT, &ddr_phy->ddrphy_reg19);
438 
439 	/* 45 degree delay */
440 	writel((DQS_DLL_45_DELAY & LEFT_CHN_RX_DQS_DELAY_TAP_MASK) <<
441 		LEFT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg8);
442 	writel((DQS_DLL_45_DELAY & RIGHT_CHN_RX_DQS_DELAY_TAP_MASK) <<
443 		RIGHT_CHN_RX_DQS_DELAY_TAP_SHIFT, &ddr_phy->ddrphy_reg11);
444 }
445 
446 static void send_command(struct rk3036_ddr_pctl *pctl,
447 			 u32 rank, u32 cmd, u32 arg)
448 {
449 	writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
450 	rockchip_udelay(1);
451 	while (readl(&pctl->mcmd) & START_CMD)
452 		;
453 }
454 
455 static void memory_init(struct rk3036_sdram_priv *priv)
456 {
457 	struct rk3036_ddr_pctl *pctl = priv->pctl;
458 
459 	send_command(pctl, 3, DESELECT_CMD, 0);
460 	rockchip_udelay(1);
461 	send_command(pctl, 3, PREA_CMD, 0);
462 	send_command(pctl, 3, MRS_CMD,
463 		     (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
464 		     (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) <<
465 		     CMD_ADDR_SHIFT);
466 
467 	send_command(pctl, 3, MRS_CMD,
468 		     (0x03 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
469 		     (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) <<
470 		     CMD_ADDR_SHIFT);
471 
472 	send_command(pctl, 3, MRS_CMD,
473 		     (0x01 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
474 		     (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) <<
475 		     CMD_ADDR_SHIFT);
476 
477 	send_command(pctl, 3, MRS_CMD,
478 		     (0x00 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT |
479 		     (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) <<
480 		     CMD_ADDR_SHIFT | DDR3_DLL_RESET);
481 
482 	send_command(pctl, 3, ZQCL_CMD, 0);
483 }
484 
485 static void data_training(struct rk3036_sdram_priv *priv)
486 {
487 	struct rk3036_ddr_phy *ddr_phy = priv->phy;
488 	struct rk3036_ddr_pctl *pctl = priv->pctl;
489 	u32 value;
490 
491 	/* disable auto refresh */
492 	value = readl(&pctl->trefi),
493 	writel(0, &pctl->trefi);
494 
495 	clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
496 			DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_CAL_START);
497 
498 	rockchip_udelay(1);
499 	while ((readl(&ddr_phy->ddrphy_reg62) & CAL_DONE_MASK) !=
500 		(HIGH_8BIT_CAL_DONE | LOW_8BIT_CAL_DONE)) {
501 		;
502 	}
503 
504 	clrsetbits_le32(&ddr_phy->ddrphy_reg2, 0x03,
505 			DQS_SQU_CAL_NORMAL_MODE | DQS_SQU_NO_CAL);
506 
507 	/*
508 	 * since data training will take about 20us, so send some auto
509 	 * refresh(about 7.8us) to complement the lost time
510 	 */
511 	send_command(pctl, 3, REF_CMD, 0);
512 	send_command(pctl, 3, REF_CMD, 0);
513 	send_command(pctl, 3, REF_CMD, 0);
514 
515 	writel(value, &pctl->trefi);
516 }
517 
518 static void move_to_config_state(struct rk3036_sdram_priv *priv)
519 {
520 	unsigned int state;
521 	struct rk3036_ddr_pctl *pctl = priv->pctl;
522 
523 	while (1) {
524 		state = readl(&pctl->stat) & PCTL_STAT_MASK;
525 		switch (state) {
526 		case LOW_POWER:
527 			writel(WAKEUP_STATE, &pctl->sctl);
528 			while ((readl(&pctl->stat) & PCTL_STAT_MASK)
529 				!= ACCESS)
530 				;
531 			/*
532 			 * If at low power state, need wakeup first, and then
533 			 * enter the config, so fallthrough
534 			 */
535 		case ACCESS:
536 			/* fallthrough */
537 		case INIT_MEM:
538 			writel(CFG_STATE, &pctl->sctl);
539 			while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
540 				;
541 			break;
542 		case CONFIG:
543 			return;
544 		default:
545 			break;
546 		}
547 	}
548 }
549 
550 static void move_to_access_state(struct rk3036_sdram_priv *priv)
551 {
552 	unsigned int state;
553 	struct rk3036_ddr_pctl *pctl = priv->pctl;
554 
555 	while (1) {
556 		state = readl(&pctl->stat) & PCTL_STAT_MASK;
557 		switch (state) {
558 		case LOW_POWER:
559 			writel(WAKEUP_STATE, &pctl->sctl);
560 			while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
561 				;
562 			break;
563 		case INIT_MEM:
564 			writel(CFG_STATE, &pctl->sctl);
565 			while ((readl(&pctl->stat) & PCTL_STAT_MASK) != CONFIG)
566 				;
567 			/* fallthrough */
568 		case CONFIG:
569 			writel(GO_STATE, &pctl->sctl);
570 			while ((readl(&pctl->stat) & PCTL_STAT_MASK) != ACCESS)
571 				;
572 			break;
573 		case ACCESS:
574 			return;
575 		default:
576 			break;
577 		}
578 	}
579 }
580 
581 static void pctl_cfg(struct rk3036_sdram_priv *priv)
582 {
583 	struct rk3036_ddr_pctl *pctl = priv->pctl;
584 	u32 burst_len;
585 	u32 reg;
586 
587 	writel(DFI_INIT_START | DFI_DATA_BYTE_DISABLE_EN, &pctl->dfistcfg0);
588 	writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, &pctl->dfistcfg1);
589 	writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
590 	writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
591 	       &pctl->dfilpcfg0);
592 
593 	writel(1, &pctl->dfitphyupdtype0);
594 	writel(0x0d, &pctl->dfitphyrdlat);
595 
596 	/* cs0 and cs1 write odt enable */
597 	writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
598 	       &pctl->dfiodtcfg);
599 
600 	/* odt write length */
601 	writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
602 
603 	/* phyupd and ctrlupd disabled */
604 	writel(0, &pctl->dfiupdcfg);
605 
606 	if ((ddr_timing.noc_timing.burstlen << 1) == 4)
607 		burst_len = MEM_BL4;
608 	else
609 		burst_len = MEM_BL8;
610 
611 	copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u,
612 		    sizeof(struct rk3036_pctl_timing));
613 	reg = readl(&pctl->tcl);
614 	writel(reg - 3, &pctl->dfitrddataen);
615 	reg = readl(&pctl->tcwl);
616 	writel(reg - 1, &pctl->dfitphywrlat);
617 
618 	writel(burst_len | (1 & TFAW_CFG_MASK) << TFAW_CFG_SHIFT |
619 			PD_EXIT_SLOW_MODE | PD_ACTIVE_POWER_DOWN |
620 			(0 & PD_IDLE_MASK) << PD_IDLE_SHIFT,
621 			&pctl->mcfg);
622 
623 	writel(RK_SETBITS(MSCH4_MAINDDR3), &priv->grf->soc_con2);
624 	setbits_le32(&pctl->scfg, HW_LOW_POWER_EN);
625 }
626 
627 static void phy_cfg(struct rk3036_sdram_priv *priv)
628 {
629 	struct rk3036_ddr_phy *ddr_phy = priv->phy;
630 	struct rk3036_service_sys *axi_bus = priv->axi_bus;
631 
632 	writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming);
633 	writel(0x3f, &axi_bus->readlatency);
634 
635 	writel(MEMORY_SELECT_DDR3 | DQS_SQU_CAL_NORMAL_MODE,
636 	       &ddr_phy->ddrphy_reg2);
637 
638 	clrsetbits_le32(&ddr_phy->ddrphy_reg3, 1, ddr_timing.phy_timing.bl);
639 	writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a);
640 	writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg16);
641 	writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg22);
642 	writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg25);
643 	writel(PHY_DRV_ODT_SET(PHY_RON_44OHM), &ddr_phy->ddrphy_reg26);
644 	writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg27);
645 	writel(PHY_DRV_ODT_SET(PHY_RTT_216OHM), &ddr_phy->ddrphy_reg28);
646 }
647 
648 void dram_cfg_rbc(struct rk3036_sdram_priv *priv)
649 {
650 	char noc_config;
651 	int i = 0;
652 	struct rk3036_ddr_config config = priv->ddr_config;
653 	struct rk3036_service_sys *axi_bus = priv->axi_bus;
654 
655 	move_to_config_state(priv);
656 
657 	/* 2bit in BIT1, 2 */
658 	if (config.rank == 2) {
659 		noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
660 			      1 << 3 | (config.col - 10);
661 		if (noc_config == ddr_cfg_2_rbc[9]) {
662 			i = 9;
663 			goto finish;
664 		} else if (noc_config == ddr_cfg_2_rbc[10]) {
665 			i = 10;
666 			goto finish;
667 		}
668 	}
669 
670 	noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 |
671 			(config.col - 10);
672 
673 	for (i = 0; i < sizeof(ddr_cfg_2_rbc); i++) {
674 		if (noc_config == ddr_cfg_2_rbc[i])
675 			goto finish;
676 	}
677 
678 	/* bank: 1 bit in BIT6,7, 1bit in BIT1, 2 */
679 	noc_config = 1 << 6 | (config.cs0_row - 13) << 4 |
680 			2 << 1 | (config.col - 10);
681 	if (noc_config == ddr_cfg_2_rbc[11]) {
682 		i = 11;
683 		goto finish;
684 	}
685 
686 	/* bank: 2bit in BIT6,7 */
687 	noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 |
688 			(config.col - 10);
689 
690 	if (noc_config == ddr_cfg_2_rbc[0])
691 		i = 0;
692 	else if (noc_config == ddr_cfg_2_rbc[12])
693 		i = 12;
694 	else if (noc_config == ddr_cfg_2_rbc[13])
695 		i = 13;
696 finish:
697 	writel(i, &axi_bus->ddrconf);
698 	move_to_access_state(priv);
699 }
700 
701 static void sdram_all_config(struct rk3036_sdram_priv *priv)
702 {
703 	u32 os_reg = 0;
704 	u32 cs1_row = 0;
705 	struct rk3036_ddr_config config = priv->ddr_config;
706 
707 	if (config.rank > 1)
708 		cs1_row = config.cs1_row - 13;
709 
710 	os_reg = config.ddr_type << DDR_TYPE_SHIFT |
711 			0 << DDR_CHN_CNT_SHIFT |
712 			(config.rank - 1) << DDR_RANK_CNT_SHIFT |
713 			(config.col - 1) << DDR_COL_SHIFT |
714 			(config.bank == 3 ? 0 : 1) << DDR_BANK_SHIFT |
715 			(config.cs0_row - 13) << DDR_CS0_ROW_SHIFT |
716 			cs1_row << DDR_CS1_ROW_SHIFT |
717 			1 << DDR_BW_SHIFT | config.bw << DDR_DIE_BW_SHIFT;
718 	writel(os_reg, &priv->grf->os_reg[1]);
719 }
720 
721 size_t sdram_size(void)
722 {
723 	u32 size, os_reg, cs0_row, cs1_row, col, bank, rank;
724 	struct rk3036_grf *grf = (void *)GRF_BASE;
725 
726 	os_reg = readl(&grf->os_reg[1]);
727 
728 	cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK);
729 	cs1_row = 13 + ((os_reg >> DDR_CS1_ROW_SHIFT) & DDR_CS1_ROW_MASK);
730 	col = 9 + ((os_reg >> DDR_COL_SHIFT) & DDR_COL_MASK);
731 	bank = 3 - ((os_reg >> DDR_BANK_SHIFT) & DDR_BANK_MASK);
732 	rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK);
733 
734 	/* row + col + bank + bw(rk3036 only support 16bit, so fix in 1) */
735 	size = 1 << (cs0_row + col + bank + 1);
736 
737 	if (rank > 1)
738 		size += size >> (cs0_row - cs1_row);
739 
740 	return size;
741 }
742 
743 void sdram_init(void)
744 {
745 	struct rk3036_sdram_priv sdram_priv;
746 
747 	sdram_priv.cru = (void *)CRU_BASE;
748 	sdram_priv.grf = (void *)GRF_BASE;
749 	sdram_priv.phy = (void *)DDR_PHY_BASE;
750 	sdram_priv.pctl = (void *)DDR_PCTL_BASE;
751 	sdram_priv.axi_bus = (void *)CPU_AXI_BUS_BASE;
752 
753 	get_ddr_config(&sdram_priv.ddr_config);
754 	sdram_all_config(&sdram_priv);
755 	rkdclk_init(&sdram_priv);
756 	phy_pctrl_reset(&sdram_priv);
757 	phy_dll_bypass_set(&sdram_priv, ddr_timing.freq);
758 	pctl_cfg(&sdram_priv);
759 	phy_cfg(&sdram_priv);
760 	writel(POWER_UP_START, &sdram_priv.pctl->powctl);
761 	while (!(readl(&sdram_priv.pctl->powstat) & POWER_UP_DONE))
762 		;
763 	memory_init(&sdram_priv);
764 	move_to_config_state(&sdram_priv);
765 	data_training(&sdram_priv);
766 	move_to_access_state(&sdram_priv);
767 	dram_cfg_rbc(&sdram_priv);
768 }
769