1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Renesas RCar Gen3 memory map tables
4  *
5  * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6  */
7 
8 #include <common.h>
9 #include <asm/armv8/mmu.h>
10 
11 #define GEN3_NR_REGIONS 16
12 
13 static struct mm_region gen3_mem_map[GEN3_NR_REGIONS] = {
14 	{
15 		.virt = 0x0UL,
16 		.phys = 0x0UL,
17 		.size = 0x40000000UL,
18 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
19 			 PTE_BLOCK_NON_SHARE |
20 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
21 	}, {
22 		.virt = 0x40000000UL,
23 		.phys = 0x40000000UL,
24 		.size = 0x80000000UL,
25 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
26 			 PTE_BLOCK_INNER_SHARE
27 	}, {
28 		.virt = 0xc0000000UL,
29 		.phys = 0xc0000000UL,
30 		.size = 0x40000000UL,
31 		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
32 			 PTE_BLOCK_NON_SHARE |
33 			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
34 	}, {
35 		.virt = 0x100000000UL,
36 		.phys = 0x100000000UL,
37 		.size = 0xf00000000UL,
38 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
39 			 PTE_BLOCK_INNER_SHARE
40 	}, {
41 		/* List terminator */
42 		0,
43 	}
44 };
45 
46 struct mm_region *mem_map = gen3_mem_map;
47 
48 DECLARE_GLOBAL_DATA_PTR;
49 
50 void enable_caches(void)
51 {
52 	u64 start, size;
53 	int bank, i = 0;
54 
55 	/* Create map for RPC access */
56 	gen3_mem_map[i].virt = 0x0ULL;
57 	gen3_mem_map[i].phys = 0x0ULL;
58 	gen3_mem_map[i].size = 0x40000000ULL;
59 	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
60 				PTE_BLOCK_NON_SHARE |
61 				PTE_BLOCK_PXN | PTE_BLOCK_UXN;
62 	i++;
63 
64 	/* Generate entires for DRAM in 32bit address space */
65 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
66 		start = gd->bd->bi_dram[bank].start;
67 		size = gd->bd->bi_dram[bank].size;
68 
69 		/* Skip empty DRAM banks */
70 		if (!size)
71 			continue;
72 
73 		/* Skip DRAM above 4 GiB */
74 		if (start >> 32ULL)
75 			continue;
76 
77 		/* Mark memory reserved by ATF as cacheable too. */
78 		if (start == 0x48000000) {
79 			start = 0x40000000ULL;
80 			size += 0x08000000ULL;
81 		}
82 
83 		gen3_mem_map[i].virt = start;
84 		gen3_mem_map[i].phys = start;
85 		gen3_mem_map[i].size = size;
86 		gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
87 					PTE_BLOCK_INNER_SHARE;
88 		i++;
89 	}
90 
91 	/* Create map for register access */
92 	gen3_mem_map[i].virt = 0xc0000000ULL;
93 	gen3_mem_map[i].phys = 0xc0000000ULL;
94 	gen3_mem_map[i].size = 0x40000000ULL;
95 	gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
96 				PTE_BLOCK_NON_SHARE |
97 				PTE_BLOCK_PXN | PTE_BLOCK_UXN;
98 	i++;
99 
100 	/* Generate entires for DRAM in 64bit address space */
101 	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
102 		start = gd->bd->bi_dram[bank].start;
103 		size = gd->bd->bi_dram[bank].size;
104 
105 		/* Skip empty DRAM banks */
106 		if (!size)
107 			continue;
108 
109 		/* Skip DRAM below 4 GiB */
110 		if (!(start >> 32ULL))
111 			continue;
112 
113 		gen3_mem_map[i].virt = start;
114 		gen3_mem_map[i].phys = start;
115 		gen3_mem_map[i].size = size;
116 		gen3_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
117 					PTE_BLOCK_INNER_SHARE;
118 		i++;
119 	}
120 
121 	/* Zero out the remaining regions. */
122 	for (; i < GEN3_NR_REGIONS; i++) {
123 		gen3_mem_map[i].virt = 0;
124 		gen3_mem_map[i].phys = 0;
125 		gen3_mem_map[i].size = 0;
126 		gen3_mem_map[i].attrs = 0;
127 	}
128 
129 	icache_enable();
130 	dcache_enable();
131 }
132