1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2581183deSNobuhiro Iwamatsu /* 3581183deSNobuhiro Iwamatsu * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h 4581183deSNobuhiro Iwamatsu * 5581183deSNobuhiro Iwamatsu * Copyright (C) 2015 Renesas Electronics Corporation 6581183deSNobuhiro Iwamatsu */ 7581183deSNobuhiro Iwamatsu 8581183deSNobuhiro Iwamatsu #ifndef __ASM_ARCH_RCAR_GEN3_BASE_H 9581183deSNobuhiro Iwamatsu #define __ASM_ARCH_RCAR_GEN3_BASE_H 10581183deSNobuhiro Iwamatsu 11581183deSNobuhiro Iwamatsu /* 12581183deSNobuhiro Iwamatsu * R-Car (R8A7750) I/O Addresses 13581183deSNobuhiro Iwamatsu */ 14581183deSNobuhiro Iwamatsu #define RWDT_BASE 0xE6020000 15581183deSNobuhiro Iwamatsu #define SWDT_BASE 0xE6030000 16581183deSNobuhiro Iwamatsu #define LBSC_BASE 0xEE220200 17581183deSNobuhiro Iwamatsu #define TMU_BASE 0xE61E0000 18581183deSNobuhiro Iwamatsu #define GPIO5_BASE 0xE6055000 19581183deSNobuhiro Iwamatsu 20581183deSNobuhiro Iwamatsu /* SCIF */ 21581183deSNobuhiro Iwamatsu #define SCIF0_BASE 0xE6E60000 22581183deSNobuhiro Iwamatsu #define SCIF1_BASE 0xE6E68000 23581183deSNobuhiro Iwamatsu #define SCIF2_BASE 0xE6E88000 24581183deSNobuhiro Iwamatsu #define SCIF3_BASE 0xE6C50000 25581183deSNobuhiro Iwamatsu #define SCIF4_BASE 0xE6C40000 26581183deSNobuhiro Iwamatsu #define SCIF5_BASE 0xE6F30000 27581183deSNobuhiro Iwamatsu 28581183deSNobuhiro Iwamatsu /* Module stop status register */ 29581183deSNobuhiro Iwamatsu #define MSTPSR0 0xE6150030 30581183deSNobuhiro Iwamatsu #define MSTPSR1 0xE6150038 31581183deSNobuhiro Iwamatsu #define MSTPSR2 0xE6150040 32581183deSNobuhiro Iwamatsu #define MSTPSR3 0xE6150048 33581183deSNobuhiro Iwamatsu #define MSTPSR4 0xE615004C 34581183deSNobuhiro Iwamatsu #define MSTPSR5 0xE615003C 35581183deSNobuhiro Iwamatsu #define MSTPSR6 0xE61501C0 36581183deSNobuhiro Iwamatsu #define MSTPSR7 0xE61501C4 37581183deSNobuhiro Iwamatsu #define MSTPSR8 0xE61509A0 38581183deSNobuhiro Iwamatsu #define MSTPSR9 0xE61509A4 39581183deSNobuhiro Iwamatsu #define MSTPSR10 0xE61509A8 40581183deSNobuhiro Iwamatsu #define MSTPSR11 0xE61509AC 41581183deSNobuhiro Iwamatsu 42581183deSNobuhiro Iwamatsu /* Realtime module stop control register */ 43581183deSNobuhiro Iwamatsu #define RMSTPCR0 0xE6150110 44581183deSNobuhiro Iwamatsu #define RMSTPCR1 0xE6150114 45581183deSNobuhiro Iwamatsu #define RMSTPCR2 0xE6150118 46581183deSNobuhiro Iwamatsu #define RMSTPCR3 0xE615011C 47581183deSNobuhiro Iwamatsu #define RMSTPCR4 0xE6150120 48581183deSNobuhiro Iwamatsu #define RMSTPCR5 0xE6150124 49581183deSNobuhiro Iwamatsu #define RMSTPCR6 0xE6150128 50581183deSNobuhiro Iwamatsu #define RMSTPCR7 0xE615012C 51581183deSNobuhiro Iwamatsu #define RMSTPCR8 0xE6150980 52581183deSNobuhiro Iwamatsu #define RMSTPCR9 0xE6150984 53581183deSNobuhiro Iwamatsu #define RMSTPCR10 0xE6150988 54581183deSNobuhiro Iwamatsu #define RMSTPCR11 0xE615098C 55581183deSNobuhiro Iwamatsu 56581183deSNobuhiro Iwamatsu /* System module stop control register */ 57581183deSNobuhiro Iwamatsu #define SMSTPCR0 0xE6150130 58581183deSNobuhiro Iwamatsu #define SMSTPCR1 0xE6150134 59581183deSNobuhiro Iwamatsu #define SMSTPCR2 0xE6150138 60581183deSNobuhiro Iwamatsu #define SMSTPCR3 0xE615013C 61581183deSNobuhiro Iwamatsu #define SMSTPCR4 0xE6150140 62581183deSNobuhiro Iwamatsu #define SMSTPCR5 0xE6150144 63581183deSNobuhiro Iwamatsu #define SMSTPCR6 0xE6150148 64581183deSNobuhiro Iwamatsu #define SMSTPCR7 0xE615014C 65581183deSNobuhiro Iwamatsu #define SMSTPCR8 0xE6150990 66581183deSNobuhiro Iwamatsu #define SMSTPCR9 0xE6150994 67581183deSNobuhiro Iwamatsu #define SMSTPCR10 0xE6150998 68581183deSNobuhiro Iwamatsu #define SMSTPCR11 0xE615099C 69581183deSNobuhiro Iwamatsu 70581183deSNobuhiro Iwamatsu /* PFC */ 71c65e46daSMarek Vasut #define PFC_PUEN5 0xE6060414 72c65e46daSMarek Vasut #define PUEN_SSI_SDATA4 BIT(17) 73581183deSNobuhiro Iwamatsu #define PFC_PUEN6 0xE6060418 74581183deSNobuhiro Iwamatsu #define PUEN_USB1_OVC (1 << 2) 75581183deSNobuhiro Iwamatsu #define PUEN_USB1_PWEN (1 << 1) 76581183deSNobuhiro Iwamatsu 7716071b1bSNobuhiro Iwamatsu /* IICDVFS (I2C) */ 7816071b1bSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_BASE0 0xE60B0000 7916071b1bSNobuhiro Iwamatsu 80581183deSNobuhiro Iwamatsu #ifndef __ASSEMBLY__ 81581183deSNobuhiro Iwamatsu #include <asm/types.h> 82581183deSNobuhiro Iwamatsu 83581183deSNobuhiro Iwamatsu /* RWDT */ 84581183deSNobuhiro Iwamatsu struct rcar_rwdt { 85581183deSNobuhiro Iwamatsu u32 rwtcnt; 86581183deSNobuhiro Iwamatsu u32 rwtcsra; 87581183deSNobuhiro Iwamatsu u32 rwtcsrb; 88581183deSNobuhiro Iwamatsu }; 89581183deSNobuhiro Iwamatsu 90581183deSNobuhiro Iwamatsu /* SWDT */ 91581183deSNobuhiro Iwamatsu struct rcar_swdt { 92581183deSNobuhiro Iwamatsu u32 swtcnt; 93581183deSNobuhiro Iwamatsu u32 swtcsra; 94581183deSNobuhiro Iwamatsu u32 swtcsrb; 95581183deSNobuhiro Iwamatsu }; 96581183deSNobuhiro Iwamatsu #endif 97581183deSNobuhiro Iwamatsu 98581183deSNobuhiro Iwamatsu #endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */ 99