1*581183deSNobuhiro Iwamatsu /* 2*581183deSNobuhiro Iwamatsu * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h 3*581183deSNobuhiro Iwamatsu * 4*581183deSNobuhiro Iwamatsu * Copyright (C) 2015 Renesas Electronics Corporation 5*581183deSNobuhiro Iwamatsu * 6*581183deSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0+ 7*581183deSNobuhiro Iwamatsu */ 8*581183deSNobuhiro Iwamatsu 9*581183deSNobuhiro Iwamatsu #ifndef __ASM_ARCH_RCAR_GEN3_BASE_H 10*581183deSNobuhiro Iwamatsu #define __ASM_ARCH_RCAR_GEN3_BASE_H 11*581183deSNobuhiro Iwamatsu 12*581183deSNobuhiro Iwamatsu /* 13*581183deSNobuhiro Iwamatsu * R-Car (R8A7750) I/O Addresses 14*581183deSNobuhiro Iwamatsu */ 15*581183deSNobuhiro Iwamatsu #define RWDT_BASE 0xE6020000 16*581183deSNobuhiro Iwamatsu #define SWDT_BASE 0xE6030000 17*581183deSNobuhiro Iwamatsu #define LBSC_BASE 0xEE220200 18*581183deSNobuhiro Iwamatsu #define TMU_BASE 0xE61E0000 19*581183deSNobuhiro Iwamatsu #define GPIO5_BASE 0xE6055000 20*581183deSNobuhiro Iwamatsu 21*581183deSNobuhiro Iwamatsu /* SCIF */ 22*581183deSNobuhiro Iwamatsu #define SCIF0_BASE 0xE6E60000 23*581183deSNobuhiro Iwamatsu #define SCIF1_BASE 0xE6E68000 24*581183deSNobuhiro Iwamatsu #define SCIF2_BASE 0xE6E88000 25*581183deSNobuhiro Iwamatsu #define SCIF3_BASE 0xE6C50000 26*581183deSNobuhiro Iwamatsu #define SCIF4_BASE 0xE6C40000 27*581183deSNobuhiro Iwamatsu #define SCIF5_BASE 0xE6F30000 28*581183deSNobuhiro Iwamatsu 29*581183deSNobuhiro Iwamatsu /* Module stop status register */ 30*581183deSNobuhiro Iwamatsu #define MSTPSR0 0xE6150030 31*581183deSNobuhiro Iwamatsu #define MSTPSR1 0xE6150038 32*581183deSNobuhiro Iwamatsu #define MSTPSR2 0xE6150040 33*581183deSNobuhiro Iwamatsu #define MSTPSR3 0xE6150048 34*581183deSNobuhiro Iwamatsu #define MSTPSR4 0xE615004C 35*581183deSNobuhiro Iwamatsu #define MSTPSR5 0xE615003C 36*581183deSNobuhiro Iwamatsu #define MSTPSR6 0xE61501C0 37*581183deSNobuhiro Iwamatsu #define MSTPSR7 0xE61501C4 38*581183deSNobuhiro Iwamatsu #define MSTPSR8 0xE61509A0 39*581183deSNobuhiro Iwamatsu #define MSTPSR9 0xE61509A4 40*581183deSNobuhiro Iwamatsu #define MSTPSR10 0xE61509A8 41*581183deSNobuhiro Iwamatsu #define MSTPSR11 0xE61509AC 42*581183deSNobuhiro Iwamatsu 43*581183deSNobuhiro Iwamatsu /* Realtime module stop control register */ 44*581183deSNobuhiro Iwamatsu #define RMSTPCR0 0xE6150110 45*581183deSNobuhiro Iwamatsu #define RMSTPCR1 0xE6150114 46*581183deSNobuhiro Iwamatsu #define RMSTPCR2 0xE6150118 47*581183deSNobuhiro Iwamatsu #define RMSTPCR3 0xE615011C 48*581183deSNobuhiro Iwamatsu #define RMSTPCR4 0xE6150120 49*581183deSNobuhiro Iwamatsu #define RMSTPCR5 0xE6150124 50*581183deSNobuhiro Iwamatsu #define RMSTPCR6 0xE6150128 51*581183deSNobuhiro Iwamatsu #define RMSTPCR7 0xE615012C 52*581183deSNobuhiro Iwamatsu #define RMSTPCR8 0xE6150980 53*581183deSNobuhiro Iwamatsu #define RMSTPCR9 0xE6150984 54*581183deSNobuhiro Iwamatsu #define RMSTPCR10 0xE6150988 55*581183deSNobuhiro Iwamatsu #define RMSTPCR11 0xE615098C 56*581183deSNobuhiro Iwamatsu 57*581183deSNobuhiro Iwamatsu /* System module stop control register */ 58*581183deSNobuhiro Iwamatsu #define SMSTPCR0 0xE6150130 59*581183deSNobuhiro Iwamatsu #define SMSTPCR1 0xE6150134 60*581183deSNobuhiro Iwamatsu #define SMSTPCR2 0xE6150138 61*581183deSNobuhiro Iwamatsu #define SMSTPCR3 0xE615013C 62*581183deSNobuhiro Iwamatsu #define SMSTPCR4 0xE6150140 63*581183deSNobuhiro Iwamatsu #define SMSTPCR5 0xE6150144 64*581183deSNobuhiro Iwamatsu #define SMSTPCR6 0xE6150148 65*581183deSNobuhiro Iwamatsu #define SMSTPCR7 0xE615014C 66*581183deSNobuhiro Iwamatsu #define SMSTPCR8 0xE6150990 67*581183deSNobuhiro Iwamatsu #define SMSTPCR9 0xE6150994 68*581183deSNobuhiro Iwamatsu #define SMSTPCR10 0xE6150998 69*581183deSNobuhiro Iwamatsu #define SMSTPCR11 0xE615099C 70*581183deSNobuhiro Iwamatsu 71*581183deSNobuhiro Iwamatsu /* SDHI */ 72*581183deSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000 73*581183deSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000 74*581183deSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 75*581183deSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 76*581183deSNobuhiro Iwamatsu 77*581183deSNobuhiro Iwamatsu /* PFC */ 78*581183deSNobuhiro Iwamatsu #define PFC_PUEN6 0xE6060418 79*581183deSNobuhiro Iwamatsu #define PUEN_USB1_OVC (1 << 2) 80*581183deSNobuhiro Iwamatsu #define PUEN_USB1_PWEN (1 << 1) 81*581183deSNobuhiro Iwamatsu 82*581183deSNobuhiro Iwamatsu #ifndef __ASSEMBLY__ 83*581183deSNobuhiro Iwamatsu #include <asm/types.h> 84*581183deSNobuhiro Iwamatsu 85*581183deSNobuhiro Iwamatsu /* RWDT */ 86*581183deSNobuhiro Iwamatsu struct rcar_rwdt { 87*581183deSNobuhiro Iwamatsu u32 rwtcnt; 88*581183deSNobuhiro Iwamatsu u32 rwtcsra; 89*581183deSNobuhiro Iwamatsu u32 rwtcsrb; 90*581183deSNobuhiro Iwamatsu }; 91*581183deSNobuhiro Iwamatsu 92*581183deSNobuhiro Iwamatsu /* SWDT */ 93*581183deSNobuhiro Iwamatsu struct rcar_swdt { 94*581183deSNobuhiro Iwamatsu u32 swtcnt; 95*581183deSNobuhiro Iwamatsu u32 swtcsra; 96*581183deSNobuhiro Iwamatsu u32 swtcsrb; 97*581183deSNobuhiro Iwamatsu }; 98*581183deSNobuhiro Iwamatsu #endif 99*581183deSNobuhiro Iwamatsu 100*581183deSNobuhiro Iwamatsu #endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */ 101