1 /*
2  * arch/arm/include/asm/arch-rmobile/r8a7793.h
3  *
4  * Copyright (C) 2014 Renesas Electronics Corporation
5  *
6  * SPDX-License-Identifier: GPL-2.0
7  */
8 
9 #ifndef __ASM_ARCH_R8A7793_H
10 #define __ASM_ARCH_R8A7793_H
11 
12 #include "rcar-base.h"
13 
14 /*
15  * R8A7793 I/O Addresses
16  */
17 
18 /* SH-I2C */
19 #define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
20 
21 /* SDHI */
22 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
23 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
24 #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
25 
26 #define DBSC3_1_QOS_R0_BASE	0xE67A1000
27 #define DBSC3_1_QOS_R1_BASE	0xE67A1100
28 #define DBSC3_1_QOS_R2_BASE	0xE67A1200
29 #define DBSC3_1_QOS_R3_BASE	0xE67A1300
30 #define DBSC3_1_QOS_R4_BASE	0xE67A1400
31 #define DBSC3_1_QOS_R5_BASE	0xE67A1500
32 #define DBSC3_1_QOS_R6_BASE	0xE67A1600
33 #define DBSC3_1_QOS_R7_BASE	0xE67A1700
34 #define DBSC3_1_QOS_R8_BASE	0xE67A1800
35 #define DBSC3_1_QOS_R9_BASE	0xE67A1900
36 #define DBSC3_1_QOS_R10_BASE	0xE67A1A00
37 #define DBSC3_1_QOS_R11_BASE	0xE67A1B00
38 #define DBSC3_1_QOS_R12_BASE	0xE67A1C00
39 #define DBSC3_1_QOS_R13_BASE	0xE67A1D00
40 #define DBSC3_1_QOS_R14_BASE	0xE67A1E00
41 #define DBSC3_1_QOS_R15_BASE	0xE67A1F00
42 #define DBSC3_1_QOS_W0_BASE	0xE67A2000
43 #define DBSC3_1_QOS_W1_BASE	0xE67A2100
44 #define DBSC3_1_QOS_W2_BASE	0xE67A2200
45 #define DBSC3_1_QOS_W3_BASE	0xE67A2300
46 #define DBSC3_1_QOS_W4_BASE	0xE67A2400
47 #define DBSC3_1_QOS_W5_BASE	0xE67A2500
48 #define DBSC3_1_QOS_W6_BASE	0xE67A2600
49 #define DBSC3_1_QOS_W7_BASE	0xE67A2700
50 #define DBSC3_1_QOS_W8_BASE	0xE67A2800
51 #define DBSC3_1_QOS_W9_BASE	0xE67A2900
52 #define DBSC3_1_QOS_W10_BASE	0xE67A2A00
53 #define DBSC3_1_QOS_W11_BASE	0xE67A2B00
54 #define DBSC3_1_QOS_W12_BASE	0xE67A2C00
55 #define DBSC3_1_QOS_W13_BASE	0xE67A2D00
56 #define DBSC3_1_QOS_W14_BASE	0xE67A2E00
57 #define DBSC3_1_QOS_W15_BASE	0xE67A2F00
58 
59 #define DBSC3_1_DBADJ2		0xE67A00C8
60 
61 /*
62  * R8A7793 I/O Product Information
63  */
64 
65 /* Module stop control/status register bits */
66 #define MSTP0_BITS	0x00640801
67 #define MSTP1_BITS	0x9B6C9B5A
68 #define MSTP2_BITS	0x100D21FC
69 #define MSTP3_BITS	0xF08CD810
70 #define MSTP4_BITS	0x800001C4
71 #define MSTP5_BITS	0x44C00046
72 #define MSTP7_BITS	0x05BFE618
73 #define MSTP8_BITS	0x40C0FE85
74 #define MSTP9_BITS	0xFF979FFF
75 #define MSTP10_BITS	0xFFFEFFE0
76 #define MSTP11_BITS	0x000001C0
77 
78 #define R8A7793_CUT_ES2X	2
79 #define IS_R8A7793_ES2() \
80 	(rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
81 
82 #endif /* __ASM_ARCH_R8A7793_H */
83