1*7a7d246dSNobuhiro Iwamatsu /* 2*7a7d246dSNobuhiro Iwamatsu * arch/arm/include/asm/arch-rmobile/r8a7791.h 3*7a7d246dSNobuhiro Iwamatsu * 4*7a7d246dSNobuhiro Iwamatsu * Copyright (C) 2013,2014 Renesas Electronics Corporation 5*7a7d246dSNobuhiro Iwamatsu * 6*7a7d246dSNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 7*7a7d246dSNobuhiro Iwamatsu */ 8*7a7d246dSNobuhiro Iwamatsu 9*7a7d246dSNobuhiro Iwamatsu #ifndef __ASM_ARCH_R8A7791_H 10*7a7d246dSNobuhiro Iwamatsu #define __ASM_ARCH_R8A7791_H 11*7a7d246dSNobuhiro Iwamatsu 12*7a7d246dSNobuhiro Iwamatsu #include "rcar-base.h" 13*7a7d246dSNobuhiro Iwamatsu /* 14*7a7d246dSNobuhiro Iwamatsu * R-Car (R8A7791) I/O Addresses 15*7a7d246dSNobuhiro Iwamatsu */ 16*7a7d246dSNobuhiro Iwamatsu 17*7a7d246dSNobuhiro Iwamatsu /* SH-I2C */ 18*7a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 19*7a7d246dSNobuhiro Iwamatsu 20*7a7d246dSNobuhiro Iwamatsu /* SDHI */ 21*7a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 22*7a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 23*7a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 24*7a7d246dSNobuhiro Iwamatsu 25*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R0_BASE 0xE67A1000 26*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R1_BASE 0xE67A1100 27*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R2_BASE 0xE67A1200 28*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R3_BASE 0xE67A1300 29*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R4_BASE 0xE67A1400 30*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R5_BASE 0xE67A1500 31*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R6_BASE 0xE67A1600 32*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R7_BASE 0xE67A1700 33*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R8_BASE 0xE67A1800 34*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R9_BASE 0xE67A1900 35*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R10_BASE 0xE67A1A00 36*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R11_BASE 0xE67A1B00 37*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R12_BASE 0xE67A1C00 38*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R13_BASE 0xE67A1D00 39*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R14_BASE 0xE67A1E00 40*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R15_BASE 0xE67A1F00 41*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W0_BASE 0xE67A2000 42*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W1_BASE 0xE67A2100 43*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W2_BASE 0xE67A2200 44*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W3_BASE 0xE67A2300 45*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W4_BASE 0xE67A2400 46*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W5_BASE 0xE67A2500 47*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W6_BASE 0xE67A2600 48*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W7_BASE 0xE67A2700 49*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W8_BASE 0xE67A2800 50*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W9_BASE 0xE67A2900 51*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W10_BASE 0xE67A2A00 52*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W11_BASE 0xE67A2B00 53*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W12_BASE 0xE67A2C00 54*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W13_BASE 0xE67A2D00 55*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 56*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 57*7a7d246dSNobuhiro Iwamatsu #define DBSC3_1_DBADJ2 0xE67A00C8 58*7a7d246dSNobuhiro Iwamatsu 59*7a7d246dSNobuhiro Iwamatsu /* Module stop control/status register bits */ 60*7a7d246dSNobuhiro Iwamatsu #define MSTP0_BITS 0x00640801 61*7a7d246dSNobuhiro Iwamatsu #define MSTP1_BITS 0x9B6C9B5A 62*7a7d246dSNobuhiro Iwamatsu #define MSTP2_BITS 0x100D21FC 63*7a7d246dSNobuhiro Iwamatsu #define MSTP3_BITS 0xF08CD810 64*7a7d246dSNobuhiro Iwamatsu #define MSTP4_BITS 0x800001C4 65*7a7d246dSNobuhiro Iwamatsu #define MSTP5_BITS 0x44C00046 66*7a7d246dSNobuhiro Iwamatsu #define MSTP7_BITS 0x05BFE618 67*7a7d246dSNobuhiro Iwamatsu #define MSTP8_BITS 0x40C0FE85 68*7a7d246dSNobuhiro Iwamatsu #define MSTP9_BITS 0xFF979FFF 69*7a7d246dSNobuhiro Iwamatsu #define MSTP10_BITS 0xFFFEFFE0 70*7a7d246dSNobuhiro Iwamatsu #define MSTP11_BITS 0x000001C0 71*7a7d246dSNobuhiro Iwamatsu 72*7a7d246dSNobuhiro Iwamatsu #define R8A7791_CUT_ES2X 2 73*7a7d246dSNobuhiro Iwamatsu #define IS_R8A7791_ES2() \ 74*7a7d246dSNobuhiro Iwamatsu (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X) 75*7a7d246dSNobuhiro Iwamatsu 76*7a7d246dSNobuhiro Iwamatsu #endif /* __ASM_ARCH_R8A7791_H */ 77