1*97775d26SManivannan Sadhasivam // SPDX-License-Identifier: GPL-2.0+ 2*97775d26SManivannan Sadhasivam /* 3*97775d26SManivannan Sadhasivam * Actions Semi S900 Memory map 4*97775d26SManivannan Sadhasivam * 5*97775d26SManivannan Sadhasivam * Copyright (C) 2015 Actions Semi Co., Ltd. 6*97775d26SManivannan Sadhasivam * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7*97775d26SManivannan Sadhasivam */ 8*97775d26SManivannan Sadhasivam 9*97775d26SManivannan Sadhasivam #include <common.h> 10*97775d26SManivannan Sadhasivam #include <asm/armv8/mmu.h> 11*97775d26SManivannan Sadhasivam 12*97775d26SManivannan Sadhasivam static struct mm_region s900_mem_map[] = { 13*97775d26SManivannan Sadhasivam { 14*97775d26SManivannan Sadhasivam .virt = 0x0UL, /* DDR */ 15*97775d26SManivannan Sadhasivam .phys = 0x0UL, /* DDR */ 16*97775d26SManivannan Sadhasivam .size = 0x80000000UL, 17*97775d26SManivannan Sadhasivam .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | 18*97775d26SManivannan Sadhasivam PTE_BLOCK_INNER_SHARE 19*97775d26SManivannan Sadhasivam }, { 20*97775d26SManivannan Sadhasivam .virt = 0xE0000000UL, /* Peripheral block */ 21*97775d26SManivannan Sadhasivam .phys = 0xE0000000UL, /* Peripheral block */ 22*97775d26SManivannan Sadhasivam .size = 0x08000000UL, 23*97775d26SManivannan Sadhasivam .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | 24*97775d26SManivannan Sadhasivam PTE_BLOCK_NON_SHARE | 25*97775d26SManivannan Sadhasivam PTE_BLOCK_PXN | PTE_BLOCK_UXN 26*97775d26SManivannan Sadhasivam }, { 27*97775d26SManivannan Sadhasivam /* List terminator */ 28*97775d26SManivannan Sadhasivam 0, 29*97775d26SManivannan Sadhasivam } 30*97775d26SManivannan Sadhasivam }; 31*97775d26SManivannan Sadhasivam 32*97775d26SManivannan Sadhasivam struct mm_region *mem_map = s900_mem_map; 33