1/*
2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
3 *
4 * (C) Copyright 2009
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 *
8 * SPDX-License-Identifier:	GPL-2.0+
9 */
10
11#include <config.h>
12#include "asm/arch/orion5x.h"
13
14/*
15 * Configuration values for SDRAM access setup
16 */
17
18#define SDRAM_CONFIG			0x3148400
19#define SDRAM_MODE			0x62
20#define SDRAM_CONTROL			0x4041000
21#define SDRAM_TIME_CTRL_LOW		0x11602220
22#define SDRAM_TIME_CTRL_HI		0x40c
23#define SDRAM_OPEN_PAGE_EN		0x0
24/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
25#define SDRAM_BANK0_SIZE		0x3ff0001
26#define SDRAM_ADDR_CTRL			0x10
27
28#define SDRAM_OP_NOP			0x05
29#define SDRAM_OP_SETMODE		0x03
30
31#define SDRAM_PAD_CTRL_WR_EN		0x80000000
32#define SDRAM_PAD_CTRL_TUNE_EN		0x00010000
33#define SDRAM_PAD_CTRL_DRVN_MASK	0x0000003f
34#define SDRAM_PAD_CTRL_DRVP_MASK	0x00000fc0
35
36/*
37 * For Guideline MEM-3 - Drive Strength value
38 */
39
40#define DDR1_PAD_STRENGTH_DEFAULT	0x00001000
41#define SDRAM_PAD_CTRL_DRV_STR_MASK	0x00003000
42
43/*
44 * For Guideline MEM-4 - DQS Reference Delay Tuning
45 */
46
47#define MSAR_ARMDDRCLCK_MASK		0x000000f0
48#define MSAR_ARMDDRCLCK_H_MASK		0x00000100
49
50#define MSAR_ARMDDRCLCK_333_167		0x00000000
51#define MSAR_ARMDDRCLCK_500_167		0x00000030
52#define MSAR_ARMDDRCLCK_667_167		0x00000060
53#define MSAR_ARMDDRCLCK_400_200_1	0x000001E0
54#define MSAR_ARMDDRCLCK_400_200		0x00000010
55#define MSAR_ARMDDRCLCK_600_200		0x00000050
56#define MSAR_ARMDDRCLCK_800_200		0x00000070
57
58#define FTDLL_DDR1_166MHZ		0x0047F001
59
60#define FTDLL_DDR1_200MHZ		0x0044D001
61
62/*
63 * Low-level init happens right after start.S has switched to SVC32,
64 * flushed and disabled caches and disabled MMU. We're still running
65 * from the boot chip select, so the first thing we should do is set
66 * up RAM for us to relocate into.
67 */
68
69.globl lowlevel_init
70
71lowlevel_init:
72
73	/* Use 'r4 as the base for internal register accesses */
74	ldr	r4, =ORION5X_REGS_PHY_BASE
75
76	/* move internal registers from the default 0xD0000000
77	 * to their intended location, defined by SoC */
78	ldr	r3, =0xD0000000
79	add	r3, r3, #0x20000
80	str	r4, [r3, #0x80]
81
82	/* Use R3 as the base for DRAM registers */
83	add	r3, r4, #0x01000
84
85	/*DDR SDRAM Initialization Control */
86	ldr	r6, =0x00000001
87	str	r6, [r3, #0x480]
88
89	/* Use R3 as the base for PCI registers */
90	add	r3, r4, #0x31000
91
92	/* Disable arbiter */
93	ldr	r6, =0x00000030
94	str	r6, [r3, #0xd00]
95
96	/* Use R3 as the base for DRAM registers */
97	add	r3, r4, #0x01000
98
99	/* set all dram windows to 0 */
100	mov	r6, #0
101	str	r6, [r3, #0x504]
102	str	r6, [r3, #0x50C]
103	str	r6, [r3, #0x514]
104	str	r6, [r3, #0x51C]
105
106	/* 1) Configure SDRAM  */
107	ldr	r6, =SDRAM_CONFIG
108	str	r6, [r3, #0x400]
109
110	/* 2) Set SDRAM Control reg */
111	ldr	r6, =SDRAM_CONTROL
112	str	r6, [r3, #0x404]
113
114	/* 3) Write SDRAM address control register */
115	ldr	r6, =SDRAM_ADDR_CTRL
116	str	r6, [r3, #0x410]
117
118	/* 4) Write SDRAM bank 0 size register */
119	ldr	r6, =SDRAM_BANK0_SIZE
120	str	r6, [r3, #0x504]
121	/* keep other banks disabled */
122
123	/* 5) Write SDRAM open pages control register */
124	ldr	r6, =SDRAM_OPEN_PAGE_EN
125	str	r6, [r3, #0x414]
126
127	/* 6) Write SDRAM timing Low register */
128	ldr	r6, =SDRAM_TIME_CTRL_LOW
129	str	r6, [r3, #0x408]
130
131	/* 7) Write SDRAM timing High register */
132	ldr	r6, =SDRAM_TIME_CTRL_HI
133	str	r6, [r3, #0x40C]
134
135	/* 8) Write SDRAM mode register */
136	/* The CPU must not attempt to change the SDRAM Mode register setting */
137	/* prior to DRAM controller completion of the DRAM initialization     */
138	/* sequence. To guarantee this restriction, it is recommended that    */
139	/* the CPU sets the SDRAM Operation register to NOP command, performs */
140	/* read polling until the register is back in Normal operation value, */
141	/* and then sets SDRAM Mode register to its new value.		      */
142
143	/* 8.1 write 'nop' to SDRAM operation */
144	ldr	r6, =SDRAM_OP_NOP
145	str	r6, [r3, #0x418]
146
147	/* 8.2 poll SDRAM operation until back in 'normal' mode.  */
1481:
149	ldr	r6, [r3, #0x418]
150	cmp	r6, #0
151	bne	1b
152
153	/* 8.3 Now its safe to write new value to SDRAM Mode register	      */
154	ldr	r6, =SDRAM_MODE
155	str	r6, [r3, #0x41C]
156
157	/* 8.4 Set new mode */
158	ldr	r6, =SDRAM_OP_SETMODE
159	str	r6, [r3, #0x418]
160
161	/* 8.5 poll SDRAM operation until back in 'normal' mode.  */
1622:
163	ldr	r6, [r3, #0x418]
164	cmp	r6, #0
165	bne	2b
166
167	/* DDR SDRAM Address/Control Pads Calibration */
168	ldr	r6, [r3, #0x4C0]
169
170	/* Set Bit [31] to make the register writable			*/
171	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
172	str	r6, [r3, #0x4C0]
173
174	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
175	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
176	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
177	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
178
179	/* Get the final N locked value of driving strength [22:17]	*/
180	mov	r1, r6
181	mov	r1, r1, LSL #9
182	mov	r1, r1, LSR #26	 /* r1[5:0]<DrvN>  = r3[22:17]<LockN>	*/
183	orr	r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN>	*/
184
185	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
186	orr	r6, r6, r1
187	str	r6, [r3, #0x4C0]
188
189	/* DDR SDRAM Data Pads Calibration				*/
190	ldr	r6, [r3, #0x4C4]
191
192	/* Set Bit [31] to make the register writable			*/
193	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
194	str	r6, [r3, #0x4C4]
195
196	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
197	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
198	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
199	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
200
201	/* Get the final N locked value of driving strength [22:17]	*/
202	mov	r1, r6
203	mov	r1, r1, LSL #9
204	mov	r1, r1, LSR #26
205	orr	r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>	*/
206
207	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
208	orr	r6, r6, r1
209
210	str	r6, [r3, #0x4C4]
211
212	/* Implement Guideline (GL# MEM-3) Drive Strength Value		*/
213	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
214
215	ldr	r1, =DDR1_PAD_STRENGTH_DEFAULT
216
217	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
218	ldr	r6, [r3, #0x4C0]
219	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
220	str	r6, [r3, #0x4C0]
221
222	/* Correct strength and disable writes again */
223	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
224	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
225	orr	r6, r6, r1
226	str	r6, [r3, #0x4C0]
227
228	/* Enable writes to DDR SDRAM Data Pads Calibration register */
229	ldr	r6, [r3, #0x4C4]
230	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
231	str	r6, [r3, #0x4C4]
232
233	/* Correct strength and disable writes again */
234	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
235	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
236	orr	r6, r6, r1
237	str	r6, [r3, #0x4C4]
238
239	/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning	*/
240	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
241
242	/* Get the "sample on reset" register for the DDR frequancy	*/
243	ldr	r3, =0x10000
244	ldr	r6, [r3, #0x010]
245	ldr	r1, =MSAR_ARMDDRCLCK_MASK
246	and	r1, r6, r1
247
248	ldr	r6, =FTDLL_DDR1_166MHZ
249	cmp	r1, #MSAR_ARMDDRCLCK_333_167
250	beq	3f
251	cmp	r1, #MSAR_ARMDDRCLCK_500_167
252	beq	3f
253	cmp	r1, #MSAR_ARMDDRCLCK_667_167
254	beq	3f
255
256	ldr	r6, =FTDLL_DDR1_200MHZ
257	cmp	r1, #MSAR_ARMDDRCLCK_400_200_1
258	beq	3f
259	cmp	r1, #MSAR_ARMDDRCLCK_400_200
260	beq	3f
261	cmp	r1, #MSAR_ARMDDRCLCK_600_200
262	beq	3f
263	cmp	r1, #MSAR_ARMDDRCLCK_800_200
264	beq	3f
265
266	ldr	r6, =0
267
2683:
269	/* Use R3 as the base for DRAM registers */
270	add	r3, r4, #0x01000
271
272	ldr	r2, [r3, #0x484]
273	orr	r2, r2, r6
274	str	r2, [r3, #0x484]
275
276	/* Return to U-boot via saved link register */
277	mov	pc, lr
278