1/*
2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
3 *
4 * (C) Copyright 2009
5 * Marvell Semiconductor <www.marvell.com>
6 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
7 *
8 * SPDX-License-Identifier:	GPL-2.0+
9 */
10
11#include <config.h>
12#include "asm/arch/orion5x.h"
13
14/*
15 * Configuration values for SDRAM access setup
16 */
17
18#define SDRAM_CONFIG			0x3148400
19#define SDRAM_MODE			0x62
20#define SDRAM_CONTROL			0x4041000
21#define SDRAM_TIME_CTRL_LOW		0x11602220
22#define SDRAM_TIME_CTRL_HI		0x40c
23#define SDRAM_OPEN_PAGE_EN		0x0
24/* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
25#define SDRAM_BANK0_SIZE		0x3ff0001
26#define SDRAM_ADDR_CTRL			0x10
27
28#define SDRAM_OP_NOP			0x05
29#define SDRAM_OP_SETMODE		0x03
30
31#define SDRAM_PAD_CTRL_WR_EN		0x80000000
32#define SDRAM_PAD_CTRL_TUNE_EN		0x00010000
33#define SDRAM_PAD_CTRL_DRVN_MASK	0x0000003f
34#define SDRAM_PAD_CTRL_DRVP_MASK	0x00000fc0
35
36/*
37 * For Guideline MEM-3 - Drive Strength value
38 */
39
40#define DDR1_PAD_STRENGTH_DEFAULT	0x00001000
41#define SDRAM_PAD_CTRL_DRV_STR_MASK	0x00003000
42
43/*
44 * For Guideline MEM-4 - DQS Reference Delay Tuning
45 */
46
47#define MSAR_ARMDDRCLCK_MASK		0x000000f0
48#define MSAR_ARMDDRCLCK_H_MASK		0x00000100
49
50#define MSAR_ARMDDRCLCK_333_167		0x00000000
51#define MSAR_ARMDDRCLCK_500_167		0x00000030
52#define MSAR_ARMDDRCLCK_667_167		0x00000060
53#define MSAR_ARMDDRCLCK_400_200_1	0x000001E0
54#define MSAR_ARMDDRCLCK_400_200		0x00000010
55#define MSAR_ARMDDRCLCK_600_200		0x00000050
56#define MSAR_ARMDDRCLCK_800_200		0x00000070
57
58#define FTDLL_DDR1_166MHZ		0x0047F001
59
60#define FTDLL_DDR1_200MHZ		0x0044D001
61
62/*
63 * Low-level init happens right after start.S has switched to SVC32,
64 * flushed and disabled caches and disabled MMU. We're still running
65 * from the boot chip select, so the first thing SPL should do is to
66 * set up the RAM to copy U-Boot into.
67 */
68
69.globl lowlevel_init
70
71lowlevel_init:
72
73#ifdef CONFIG_SPL_BUILD
74
75	/* Use 'r4 as the base for internal register accesses */
76	ldr	r4, =ORION5X_REGS_PHY_BASE
77
78	/* move internal registers from the default 0xD0000000
79	 * to their intended location, defined by SoC */
80	ldr	r3, =0xD0000000
81	add	r3, r3, #0x20000
82	str	r4, [r3, #0x80]
83
84	/* Use R3 as the base for DRAM registers */
85	add	r3, r4, #0x01000
86
87	/*DDR SDRAM Initialization Control */
88	ldr	r6, =0x00000001
89	str	r6, [r3, #0x480]
90
91	/* Use R3 as the base for PCI registers */
92	add	r3, r4, #0x31000
93
94	/* Disable arbiter */
95	ldr	r6, =0x00000030
96	str	r6, [r3, #0xd00]
97
98	/* Use R3 as the base for DRAM registers */
99	add	r3, r4, #0x01000
100
101	/* set all dram windows to 0 */
102	mov	r6, #0
103	str	r6, [r3, #0x504]
104	str	r6, [r3, #0x50C]
105	str	r6, [r3, #0x514]
106	str	r6, [r3, #0x51C]
107
108	/* 1) Configure SDRAM  */
109	ldr	r6, =SDRAM_CONFIG
110	str	r6, [r3, #0x400]
111
112	/* 2) Set SDRAM Control reg */
113	ldr	r6, =SDRAM_CONTROL
114	str	r6, [r3, #0x404]
115
116	/* 3) Write SDRAM address control register */
117	ldr	r6, =SDRAM_ADDR_CTRL
118	str	r6, [r3, #0x410]
119
120	/* 4) Write SDRAM bank 0 size register */
121	ldr	r6, =SDRAM_BANK0_SIZE
122	str	r6, [r3, #0x504]
123	/* keep other banks disabled */
124
125	/* 5) Write SDRAM open pages control register */
126	ldr	r6, =SDRAM_OPEN_PAGE_EN
127	str	r6, [r3, #0x414]
128
129	/* 6) Write SDRAM timing Low register */
130	ldr	r6, =SDRAM_TIME_CTRL_LOW
131	str	r6, [r3, #0x408]
132
133	/* 7) Write SDRAM timing High register */
134	ldr	r6, =SDRAM_TIME_CTRL_HI
135	str	r6, [r3, #0x40C]
136
137	/* 8) Write SDRAM mode register */
138	/* The CPU must not attempt to change the SDRAM Mode register setting */
139	/* prior to DRAM controller completion of the DRAM initialization     */
140	/* sequence. To guarantee this restriction, it is recommended that    */
141	/* the CPU sets the SDRAM Operation register to NOP command, performs */
142	/* read polling until the register is back in Normal operation value, */
143	/* and then sets SDRAM Mode register to its new value.		      */
144
145	/* 8.1 write 'nop' to SDRAM operation */
146	ldr	r6, =SDRAM_OP_NOP
147	str	r6, [r3, #0x418]
148
149	/* 8.2 poll SDRAM operation until back in 'normal' mode.  */
1501:
151	ldr	r6, [r3, #0x418]
152	cmp	r6, #0
153	bne	1b
154
155	/* 8.3 Now its safe to write new value to SDRAM Mode register	      */
156	ldr	r6, =SDRAM_MODE
157	str	r6, [r3, #0x41C]
158
159	/* 8.4 Set new mode */
160	ldr	r6, =SDRAM_OP_SETMODE
161	str	r6, [r3, #0x418]
162
163	/* 8.5 poll SDRAM operation until back in 'normal' mode.  */
1642:
165	ldr	r6, [r3, #0x418]
166	cmp	r6, #0
167	bne	2b
168
169	/* DDR SDRAM Address/Control Pads Calibration */
170	ldr	r6, [r3, #0x4C0]
171
172	/* Set Bit [31] to make the register writable			*/
173	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
174	str	r6, [r3, #0x4C0]
175
176	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
177	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
178	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
179	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
180
181	/* Get the final N locked value of driving strength [22:17]	*/
182	mov	r1, r6
183	mov	r1, r1, LSL #9
184	mov	r1, r1, LSR #26	 /* r1[5:0]<DrvN>  = r3[22:17]<LockN>	*/
185	orr	r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN>	*/
186
187	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
188	orr	r6, r6, r1
189	str	r6, [r3, #0x4C0]
190
191	/* DDR SDRAM Data Pads Calibration				*/
192	ldr	r6, [r3, #0x4C4]
193
194	/* Set Bit [31] to make the register writable			*/
195	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
196	str	r6, [r3, #0x4C4]
197
198	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
199	bic	r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
200	bic	r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
201	bic	r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
202
203	/* Get the final N locked value of driving strength [22:17]	*/
204	mov	r1, r6
205	mov	r1, r1, LSL #9
206	mov	r1, r1, LSR #26
207	orr	r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN>	*/
208
209	/* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6]	*/
210	orr	r6, r6, r1
211
212	str	r6, [r3, #0x4C4]
213
214	/* Implement Guideline (GL# MEM-3) Drive Strength Value		*/
215	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
216
217	ldr	r1, =DDR1_PAD_STRENGTH_DEFAULT
218
219	/* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
220	ldr	r6, [r3, #0x4C0]
221	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
222	str	r6, [r3, #0x4C0]
223
224	/* Correct strength and disable writes again */
225	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
226	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
227	orr	r6, r6, r1
228	str	r6, [r3, #0x4C0]
229
230	/* Enable writes to DDR SDRAM Data Pads Calibration register */
231	ldr	r6, [r3, #0x4C4]
232	orr	r6, r6, #SDRAM_PAD_CTRL_WR_EN
233	str	r6, [r3, #0x4C4]
234
235	/* Correct strength and disable writes again */
236	bic	r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
237	bic	r6, r6, #SDRAM_PAD_CTRL_WR_EN
238	orr	r6, r6, r1
239	str	r6, [r3, #0x4C4]
240
241	/* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning	*/
242	/* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0		*/
243
244	/* Get the "sample on reset" register for the DDR frequancy	*/
245	ldr	r3, =0x10000
246	ldr	r6, [r3, #0x010]
247	ldr	r1, =MSAR_ARMDDRCLCK_MASK
248	and	r1, r6, r1
249
250	ldr	r6, =FTDLL_DDR1_166MHZ
251	cmp	r1, #MSAR_ARMDDRCLCK_333_167
252	beq	3f
253	cmp	r1, #MSAR_ARMDDRCLCK_500_167
254	beq	3f
255	cmp	r1, #MSAR_ARMDDRCLCK_667_167
256	beq	3f
257
258	ldr	r6, =FTDLL_DDR1_200MHZ
259	cmp	r1, #MSAR_ARMDDRCLCK_400_200_1
260	beq	3f
261	cmp	r1, #MSAR_ARMDDRCLCK_400_200
262	beq	3f
263	cmp	r1, #MSAR_ARMDDRCLCK_600_200
264	beq	3f
265	cmp	r1, #MSAR_ARMDDRCLCK_800_200
266	beq	3f
267
268	ldr	r6, =0
269
2703:
271	/* Use R3 as the base for DRAM registers */
272	add	r3, r4, #0x01000
273
274	ldr	r2, [r3, #0x484]
275	orr	r2, r2, r6
276	str	r2, [r3, #0x484]
277
278	/* enable for 2 GB DDR; detection should find out real amount */
279	sub	r6, r6, r6
280	str	r6, [r3, #0x500]
281	ldr	r6, =0x7fff0001
282	str	r6, [r3, #0x504]
283
284#endif /* CONFIG_SPL_BUILD */
285
286	/* Return to U-Boot via saved link register */
287	mov	pc, lr
288