1 /* 2 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3 * 4 * Based on original Kirorion5x_ood support which is 5 * (C) Copyright 2009 6 * Marvell Semiconductor <www.marvell.com> 7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef _ORION5X_CPU_H 13 #define _ORION5X_CPU_H 14 15 #include <asm/system.h> 16 17 #ifndef __ASSEMBLY__ 18 19 #define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ 20 | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) 21 22 #define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ 23 ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) 24 25 enum memory_bank { 26 BANK0, 27 BANK1, 28 BANK2, 29 BANK3 30 }; 31 32 enum orion5x_cpu_winen { 33 ORION5X_WIN_DISABLE, 34 ORION5X_WIN_ENABLE 35 }; 36 37 enum orion5x_cpu_target { 38 ORION5X_TARGET_DRAM = 0, 39 ORION5X_TARGET_DEVICE = 1, 40 ORION5X_TARGET_PCI = 3, 41 ORION5X_TARGET_PCIE = 4, 42 ORION5X_TARGET_SASRAM = 9 43 }; 44 45 enum orion5x_cpu_attrib { 46 ORION5X_ATTR_DRAM_CS0 = 0x0e, 47 ORION5X_ATTR_DRAM_CS1 = 0x0d, 48 ORION5X_ATTR_DRAM_CS2 = 0x0b, 49 ORION5X_ATTR_DRAM_CS3 = 0x07, 50 ORION5X_ATTR_PCI_MEM = 0x59, 51 ORION5X_ATTR_PCI_IO = 0x51, 52 ORION5X_ATTR_PCIE_MEM = 0x59, 53 ORION5X_ATTR_PCIE_IO = 0x51, 54 ORION5X_ATTR_SASRAM = 0x00, 55 ORION5X_ATTR_DEV_CS0 = 0x1e, 56 ORION5X_ATTR_DEV_CS1 = 0x1d, 57 ORION5X_ATTR_DEV_CS2 = 0x1b, 58 ORION5X_ATTR_BOOTROM = 0x0f 59 }; 60 61 /* 62 * Device Address MAP BAR values 63 * 64 * All addresses and sizes not defined by board code 65 * will be given default values here. 66 */ 67 68 #if !defined (ORION5X_ADR_PCIE_MEM) 69 #define ORION5X_ADR_PCIE_MEM 0x90000000 70 #endif 71 72 #if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO) 73 #define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000 74 #endif 75 76 #if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI) 77 #define ORION5X_ADR_PCIE_MEM_REMAP_HI 0 78 #endif 79 80 #if !defined (ORION5X_SZ_PCIE_MEM) 81 #define ORION5X_SZ_PCIE_MEM (128*1024*1024) 82 #endif 83 84 #if !defined (ORION5X_ADR_PCIE_IO) 85 #define ORION5X_ADR_PCIE_IO 0xf0000000 86 #endif 87 88 #if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) 89 #define ORION5X_ADR_PCIE_IO_REMAP_LO 0xf0000000 90 #endif 91 92 #if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) 93 #define ORION5X_ADR_PCIE_IO_REMAP_HI 0 94 #endif 95 96 #if !defined (ORION5X_SZ_PCIE_IO) 97 #define ORION5X_SZ_PCIE_IO (64*1024) 98 #endif 99 100 #if !defined (ORION5X_ADR_PCI_MEM) 101 #define ORION5X_ADR_PCI_MEM 0x98000000 102 #endif 103 104 #if !defined (ORION5X_SZ_PCI_MEM) 105 #define ORION5X_SZ_PCI_MEM (128*1024*1024) 106 #endif 107 108 #if !defined (ORION5X_ADR_PCI_IO) 109 #define ORION5X_ADR_PCI_IO 0xf0100000 110 #endif 111 112 #if !defined (ORION5X_SZ_PCI_IO) 113 #define ORION5X_SZ_PCI_IO (64*1024) 114 #endif 115 116 #if !defined (ORION5X_ADR_DEV_CS0) 117 #define ORION5X_ADR_DEV_CS0 0xfa000000 118 #endif 119 120 #if !defined (ORION5X_SZ_DEV_CS0) 121 #define ORION5X_SZ_DEV_CS0 (2*1024*1024) 122 #endif 123 124 #if !defined (ORION5X_ADR_DEV_CS1) 125 #define ORION5X_ADR_DEV_CS1 0xf8000000 126 #endif 127 128 #if !defined (ORION5X_SZ_DEV_CS1) 129 #define ORION5X_SZ_DEV_CS1 (32*1024*1024) 130 #endif 131 132 #if !defined (ORION5X_ADR_DEV_CS2) 133 #define ORION5X_ADR_DEV_CS2 0xfa800000 134 #endif 135 136 #if !defined (ORION5X_SZ_DEV_CS2) 137 #define ORION5X_SZ_DEV_CS2 (1*1024*1024) 138 #endif 139 140 #if !defined (ORION5X_ADR_BOOTROM) 141 #define ORION5X_ADR_BOOTROM 0xFFF80000 142 #endif 143 144 #if !defined (ORION5X_SZ_BOOTROM) 145 #define ORION5X_SZ_BOOTROM (512*1024) 146 #endif 147 148 /* 149 * PCIE registers are used for SoC device ID and revision 150 */ 151 #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) 152 #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) 153 154 /* 155 * The following definitions are intended for identifying 156 * the real device and revision on which u-boot is running 157 * even if it was compiled only for a specific one. Thus, 158 * these constants must not be considered chip-specific. 159 */ 160 161 /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ 162 #define MV88F5181_DEV_ID 0x5181 163 #define MV88F5181_REV_B1 3 164 #define MV88F5181L_REV_A0 8 165 #define MV88F5181L_REV_A1 9 166 /* Orion-NAS (88F5182) */ 167 #define MV88F5182_DEV_ID 0x5182 168 #define MV88F5182_REV_A2 2 169 /* Orion-2 (88F5281) */ 170 #define MV88F5281_DEV_ID 0x5281 171 #define MV88F5281_REV_D0 4 172 #define MV88F5281_REV_D1 5 173 #define MV88F5281_REV_D2 6 174 /* Orion-1-90 (88F6183) */ 175 #define MV88F6183_DEV_ID 0x6183 176 #define MV88F6183_REV_B0 3 177 178 /* 179 * read feroceon core extra feature register 180 * using co-proc instruction 181 */ 182 static inline unsigned int readfr_extra_feature_reg(void) 183 { 184 unsigned int val; 185 asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r" 186 (val) : : "cc"); 187 return val; 188 } 189 190 /* 191 * write feroceon core extra feature register 192 * using co-proc instruction 193 */ 194 static inline void writefr_extra_feature_reg(unsigned int val) 195 { 196 asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r" 197 (val) : "cc"); 198 isb(); 199 } 200 201 /* 202 * AHB to Mbus Bridge Registers 203 * Source: 88F5182 User Manual, Appendix A, section A.4 204 * Note: only windows 0 and 1 have remap capability. 205 */ 206 struct orion5x_win_registers { 207 u32 ctrl; 208 u32 base; 209 u32 remap_lo; 210 u32 remap_hi; 211 }; 212 213 /* 214 * CPU control and status Registers 215 * Source: 88F5182 User Manual, Appendix A, section A.4 216 */ 217 struct orion5x_cpu_registers { 218 u32 config; /*0x20100 */ 219 u32 ctrl_stat; /*0x20104 */ 220 u32 rstoutn_mask; /* 0x20108 */ 221 u32 sys_soft_rst; /* 0x2010C */ 222 u32 ahb_mbus_cause_irq; /* 0x20110 */ 223 u32 ahb_mbus_mask_irq; /* 0x20114 */ 224 }; 225 226 /* 227 * DDR SDRAM Controller Address Decode Registers 228 * Source: 88F5182 User Manual, Appendix A, section A.5.1 229 */ 230 struct orion5x_ddr_addr_decode_registers { 231 u32 base; 232 u32 size; 233 }; 234 235 /* 236 * functions 237 */ 238 u32 orion5x_device_id(void); 239 u32 orion5x_device_rev(void); 240 unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); 241 void timer_init_r(void); 242 #endif /* __ASSEMBLY__ */ 243 #endif /* _ORION5X_CPU_H */ 244