1*fd697ecfSMasahiro Yamada /* 2*fd697ecfSMasahiro Yamada * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 3*fd697ecfSMasahiro Yamada * 4*fd697ecfSMasahiro Yamada * Based on original Kirorion5x_ood support which is 5*fd697ecfSMasahiro Yamada * (C) Copyright 2009 6*fd697ecfSMasahiro Yamada * Marvell Semiconductor <www.marvell.com> 7*fd697ecfSMasahiro Yamada * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 8*fd697ecfSMasahiro Yamada * 9*fd697ecfSMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ 10*fd697ecfSMasahiro Yamada */ 11*fd697ecfSMasahiro Yamada 12*fd697ecfSMasahiro Yamada #ifndef _ORION5X_CPU_H 13*fd697ecfSMasahiro Yamada #define _ORION5X_CPU_H 14*fd697ecfSMasahiro Yamada 15*fd697ecfSMasahiro Yamada #include <asm/system.h> 16*fd697ecfSMasahiro Yamada 17*fd697ecfSMasahiro Yamada #ifndef __ASSEMBLY__ 18*fd697ecfSMasahiro Yamada 19*fd697ecfSMasahiro Yamada #define ORION5X_CPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ 20*fd697ecfSMasahiro Yamada | (attr << 8) | (orion5x_winctrl_calcsize(size) << 16)) 21*fd697ecfSMasahiro Yamada 22*fd697ecfSMasahiro Yamada #define ORION5XGBE_PORT_SERIAL_CONTROL1_REG(_x) \ 23*fd697ecfSMasahiro Yamada ((_x ? ORION5X_EGIGA0_BASE : ORION5X_EGIGA1_BASE) + 0x44c) 24*fd697ecfSMasahiro Yamada 25*fd697ecfSMasahiro Yamada enum memory_bank { 26*fd697ecfSMasahiro Yamada BANK0, 27*fd697ecfSMasahiro Yamada BANK1, 28*fd697ecfSMasahiro Yamada BANK2, 29*fd697ecfSMasahiro Yamada BANK3 30*fd697ecfSMasahiro Yamada }; 31*fd697ecfSMasahiro Yamada 32*fd697ecfSMasahiro Yamada enum orion5x_cpu_winen { 33*fd697ecfSMasahiro Yamada ORION5X_WIN_DISABLE, 34*fd697ecfSMasahiro Yamada ORION5X_WIN_ENABLE 35*fd697ecfSMasahiro Yamada }; 36*fd697ecfSMasahiro Yamada 37*fd697ecfSMasahiro Yamada enum orion5x_cpu_target { 38*fd697ecfSMasahiro Yamada ORION5X_TARGET_DRAM = 0, 39*fd697ecfSMasahiro Yamada ORION5X_TARGET_DEVICE = 1, 40*fd697ecfSMasahiro Yamada ORION5X_TARGET_PCI = 3, 41*fd697ecfSMasahiro Yamada ORION5X_TARGET_PCIE = 4, 42*fd697ecfSMasahiro Yamada ORION5X_TARGET_SASRAM = 9 43*fd697ecfSMasahiro Yamada }; 44*fd697ecfSMasahiro Yamada 45*fd697ecfSMasahiro Yamada enum orion5x_cpu_attrib { 46*fd697ecfSMasahiro Yamada ORION5X_ATTR_DRAM_CS0 = 0x0e, 47*fd697ecfSMasahiro Yamada ORION5X_ATTR_DRAM_CS1 = 0x0d, 48*fd697ecfSMasahiro Yamada ORION5X_ATTR_DRAM_CS2 = 0x0b, 49*fd697ecfSMasahiro Yamada ORION5X_ATTR_DRAM_CS3 = 0x07, 50*fd697ecfSMasahiro Yamada ORION5X_ATTR_PCI_MEM = 0x59, 51*fd697ecfSMasahiro Yamada ORION5X_ATTR_PCI_IO = 0x51, 52*fd697ecfSMasahiro Yamada ORION5X_ATTR_PCIE_MEM = 0x59, 53*fd697ecfSMasahiro Yamada ORION5X_ATTR_PCIE_IO = 0x51, 54*fd697ecfSMasahiro Yamada ORION5X_ATTR_SASRAM = 0x00, 55*fd697ecfSMasahiro Yamada ORION5X_ATTR_DEV_CS0 = 0x1e, 56*fd697ecfSMasahiro Yamada ORION5X_ATTR_DEV_CS1 = 0x1d, 57*fd697ecfSMasahiro Yamada ORION5X_ATTR_DEV_CS2 = 0x1b, 58*fd697ecfSMasahiro Yamada ORION5X_ATTR_BOOTROM = 0x0f 59*fd697ecfSMasahiro Yamada }; 60*fd697ecfSMasahiro Yamada 61*fd697ecfSMasahiro Yamada /* 62*fd697ecfSMasahiro Yamada * Device Address MAP BAR values 63*fd697ecfSMasahiro Yamada * 64*fd697ecfSMasahiro Yamada * All addresses and sizes not defined by board code 65*fd697ecfSMasahiro Yamada * will be given default values here. 66*fd697ecfSMasahiro Yamada */ 67*fd697ecfSMasahiro Yamada 68*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCIE_MEM) 69*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCIE_MEM 0x90000000 70*fd697ecfSMasahiro Yamada #endif 71*fd697ecfSMasahiro Yamada 72*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCIE_MEM_REMAP_LO) 73*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCIE_MEM_REMAP_LO 0x90000000 74*fd697ecfSMasahiro Yamada #endif 75*fd697ecfSMasahiro Yamada 76*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCIE_MEM_REMAP_HI) 77*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCIE_MEM_REMAP_HI 0 78*fd697ecfSMasahiro Yamada #endif 79*fd697ecfSMasahiro Yamada 80*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_PCIE_MEM) 81*fd697ecfSMasahiro Yamada #define ORION5X_SZ_PCIE_MEM (128*1024*1024) 82*fd697ecfSMasahiro Yamada #endif 83*fd697ecfSMasahiro Yamada 84*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCIE_IO) 85*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCIE_IO 0xf0000000 86*fd697ecfSMasahiro Yamada #endif 87*fd697ecfSMasahiro Yamada 88*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCIE_IO_REMAP_LO) 89*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCIE_IO_REMAP_LO 0x90000000 90*fd697ecfSMasahiro Yamada #endif 91*fd697ecfSMasahiro Yamada 92*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCIE_IO_REMAP_HI) 93*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCIE_IO_REMAP_HI 0 94*fd697ecfSMasahiro Yamada #endif 95*fd697ecfSMasahiro Yamada 96*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_PCIE_IO) 97*fd697ecfSMasahiro Yamada #define ORION5X_SZ_PCIE_IO (64*1024) 98*fd697ecfSMasahiro Yamada #endif 99*fd697ecfSMasahiro Yamada 100*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCI_MEM) 101*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCI_MEM 0x98000000 102*fd697ecfSMasahiro Yamada #endif 103*fd697ecfSMasahiro Yamada 104*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_PCI_MEM) 105*fd697ecfSMasahiro Yamada #define ORION5X_SZ_PCI_MEM (128*1024*1024) 106*fd697ecfSMasahiro Yamada #endif 107*fd697ecfSMasahiro Yamada 108*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_PCI_IO) 109*fd697ecfSMasahiro Yamada #define ORION5X_ADR_PCI_IO 0xf0100000 110*fd697ecfSMasahiro Yamada #endif 111*fd697ecfSMasahiro Yamada 112*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_PCI_IO) 113*fd697ecfSMasahiro Yamada #define ORION5X_SZ_PCI_IO (64*1024) 114*fd697ecfSMasahiro Yamada #endif 115*fd697ecfSMasahiro Yamada 116*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_DEV_CS0) 117*fd697ecfSMasahiro Yamada #define ORION5X_ADR_DEV_CS0 0xfa000000 118*fd697ecfSMasahiro Yamada #endif 119*fd697ecfSMasahiro Yamada 120*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_DEV_CS0) 121*fd697ecfSMasahiro Yamada #define ORION5X_SZ_DEV_CS0 (2*1024*1024) 122*fd697ecfSMasahiro Yamada #endif 123*fd697ecfSMasahiro Yamada 124*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_DEV_CS1) 125*fd697ecfSMasahiro Yamada #define ORION5X_ADR_DEV_CS1 0xf8000000 126*fd697ecfSMasahiro Yamada #endif 127*fd697ecfSMasahiro Yamada 128*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_DEV_CS1) 129*fd697ecfSMasahiro Yamada #define ORION5X_SZ_DEV_CS1 (32*1024*1024) 130*fd697ecfSMasahiro Yamada #endif 131*fd697ecfSMasahiro Yamada 132*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_DEV_CS2) 133*fd697ecfSMasahiro Yamada #define ORION5X_ADR_DEV_CS2 0xfa800000 134*fd697ecfSMasahiro Yamada #endif 135*fd697ecfSMasahiro Yamada 136*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_DEV_CS2) 137*fd697ecfSMasahiro Yamada #define ORION5X_SZ_DEV_CS2 (1*1024*1024) 138*fd697ecfSMasahiro Yamada #endif 139*fd697ecfSMasahiro Yamada 140*fd697ecfSMasahiro Yamada #if !defined (ORION5X_ADR_BOOTROM) 141*fd697ecfSMasahiro Yamada #define ORION5X_ADR_BOOTROM 0xFFF80000 142*fd697ecfSMasahiro Yamada #endif 143*fd697ecfSMasahiro Yamada 144*fd697ecfSMasahiro Yamada #if !defined (ORION5X_SZ_BOOTROM) 145*fd697ecfSMasahiro Yamada #define ORION5X_SZ_BOOTROM (512*1024) 146*fd697ecfSMasahiro Yamada #endif 147*fd697ecfSMasahiro Yamada 148*fd697ecfSMasahiro Yamada /* 149*fd697ecfSMasahiro Yamada * PCIE registers are used for SoC device ID and revision 150*fd697ecfSMasahiro Yamada */ 151*fd697ecfSMasahiro Yamada #define PCIE_DEV_ID_OFF (ORION5X_REG_PCIE_BASE + 0x0000) 152*fd697ecfSMasahiro Yamada #define PCIE_DEV_REV_OFF (ORION5X_REG_PCIE_BASE + 0x0008) 153*fd697ecfSMasahiro Yamada 154*fd697ecfSMasahiro Yamada /* 155*fd697ecfSMasahiro Yamada * The following definitions are intended for identifying 156*fd697ecfSMasahiro Yamada * the real device and revision on which u-boot is running 157*fd697ecfSMasahiro Yamada * even if it was compiled only for a specific one. Thus, 158*fd697ecfSMasahiro Yamada * these constants must not be considered chip-specific. 159*fd697ecfSMasahiro Yamada */ 160*fd697ecfSMasahiro Yamada 161*fd697ecfSMasahiro Yamada /* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */ 162*fd697ecfSMasahiro Yamada #define MV88F5181_DEV_ID 0x5181 163*fd697ecfSMasahiro Yamada #define MV88F5181_REV_B1 3 164*fd697ecfSMasahiro Yamada #define MV88F5181L_REV_A0 8 165*fd697ecfSMasahiro Yamada #define MV88F5181L_REV_A1 9 166*fd697ecfSMasahiro Yamada /* Orion-NAS (88F5182) */ 167*fd697ecfSMasahiro Yamada #define MV88F5182_DEV_ID 0x5182 168*fd697ecfSMasahiro Yamada #define MV88F5182_REV_A2 2 169*fd697ecfSMasahiro Yamada /* Orion-2 (88F5281) */ 170*fd697ecfSMasahiro Yamada #define MV88F5281_DEV_ID 0x5281 171*fd697ecfSMasahiro Yamada #define MV88F5281_REV_D0 4 172*fd697ecfSMasahiro Yamada #define MV88F5281_REV_D1 5 173*fd697ecfSMasahiro Yamada #define MV88F5281_REV_D2 6 174*fd697ecfSMasahiro Yamada /* Orion-1-90 (88F6183) */ 175*fd697ecfSMasahiro Yamada #define MV88F6183_DEV_ID 0x6183 176*fd697ecfSMasahiro Yamada #define MV88F6183_REV_B0 3 177*fd697ecfSMasahiro Yamada 178*fd697ecfSMasahiro Yamada /* 179*fd697ecfSMasahiro Yamada * read feroceon core extra feature register 180*fd697ecfSMasahiro Yamada * using co-proc instruction 181*fd697ecfSMasahiro Yamada */ 182*fd697ecfSMasahiro Yamada static inline unsigned int readfr_extra_feature_reg(void) 183*fd697ecfSMasahiro Yamada { 184*fd697ecfSMasahiro Yamada unsigned int val; 185*fd697ecfSMasahiro Yamada asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr" : "=r" 186*fd697ecfSMasahiro Yamada (val) : : "cc"); 187*fd697ecfSMasahiro Yamada return val; 188*fd697ecfSMasahiro Yamada } 189*fd697ecfSMasahiro Yamada 190*fd697ecfSMasahiro Yamada /* 191*fd697ecfSMasahiro Yamada * write feroceon core extra feature register 192*fd697ecfSMasahiro Yamada * using co-proc instruction 193*fd697ecfSMasahiro Yamada */ 194*fd697ecfSMasahiro Yamada static inline void writefr_extra_feature_reg(unsigned int val) 195*fd697ecfSMasahiro Yamada { 196*fd697ecfSMasahiro Yamada asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr" : : "r" 197*fd697ecfSMasahiro Yamada (val) : "cc"); 198*fd697ecfSMasahiro Yamada isb(); 199*fd697ecfSMasahiro Yamada } 200*fd697ecfSMasahiro Yamada 201*fd697ecfSMasahiro Yamada /* 202*fd697ecfSMasahiro Yamada * AHB to Mbus Bridge Registers 203*fd697ecfSMasahiro Yamada * Source: 88F5182 User Manual, Appendix A, section A.4 204*fd697ecfSMasahiro Yamada * Note: only windows 0 and 1 have remap capability. 205*fd697ecfSMasahiro Yamada */ 206*fd697ecfSMasahiro Yamada struct orion5x_win_registers { 207*fd697ecfSMasahiro Yamada u32 ctrl; 208*fd697ecfSMasahiro Yamada u32 base; 209*fd697ecfSMasahiro Yamada u32 remap_lo; 210*fd697ecfSMasahiro Yamada u32 remap_hi; 211*fd697ecfSMasahiro Yamada }; 212*fd697ecfSMasahiro Yamada 213*fd697ecfSMasahiro Yamada /* 214*fd697ecfSMasahiro Yamada * CPU control and status Registers 215*fd697ecfSMasahiro Yamada * Source: 88F5182 User Manual, Appendix A, section A.4 216*fd697ecfSMasahiro Yamada */ 217*fd697ecfSMasahiro Yamada struct orion5x_cpu_registers { 218*fd697ecfSMasahiro Yamada u32 config; /*0x20100 */ 219*fd697ecfSMasahiro Yamada u32 ctrl_stat; /*0x20104 */ 220*fd697ecfSMasahiro Yamada u32 rstoutn_mask; /* 0x20108 */ 221*fd697ecfSMasahiro Yamada u32 sys_soft_rst; /* 0x2010C */ 222*fd697ecfSMasahiro Yamada u32 ahb_mbus_cause_irq; /* 0x20110 */ 223*fd697ecfSMasahiro Yamada u32 ahb_mbus_mask_irq; /* 0x20114 */ 224*fd697ecfSMasahiro Yamada }; 225*fd697ecfSMasahiro Yamada 226*fd697ecfSMasahiro Yamada /* 227*fd697ecfSMasahiro Yamada * DDR SDRAM Controller Address Decode Registers 228*fd697ecfSMasahiro Yamada * Source: 88F5182 User Manual, Appendix A, section A.5.1 229*fd697ecfSMasahiro Yamada */ 230*fd697ecfSMasahiro Yamada struct orion5x_ddr_addr_decode_registers { 231*fd697ecfSMasahiro Yamada u32 base; 232*fd697ecfSMasahiro Yamada u32 size; 233*fd697ecfSMasahiro Yamada }; 234*fd697ecfSMasahiro Yamada 235*fd697ecfSMasahiro Yamada /* 236*fd697ecfSMasahiro Yamada * functions 237*fd697ecfSMasahiro Yamada */ 238*fd697ecfSMasahiro Yamada u32 orion5x_device_id(void); 239*fd697ecfSMasahiro Yamada u32 orion5x_device_rev(void); 240*fd697ecfSMasahiro Yamada unsigned int orion5x_winctrl_calcsize(unsigned int sizeval); 241*fd697ecfSMasahiro Yamada void timer_init_r(void); 242*fd697ecfSMasahiro Yamada #endif /* __ASSEMBLY__ */ 243*fd697ecfSMasahiro Yamada #endif /* _ORION5X_CPU_H */ 244