1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> 4 * 5 * Based on original Kirkwood support which is 6 * (C) Copyright 2009 7 * Marvell Semiconductor <www.marvell.com> 8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 */ 10 11 #include <common.h> 12 #include <config.h> 13 #include <asm/arch/cpu.h> 14 15 DECLARE_GLOBAL_DATA_PTR; 16 17 /* 18 * orion5x_sdram_bar - reads SDRAM Base Address Register 19 */ 20 u32 orion5x_sdram_bar(enum memory_bank bank) 21 { 22 struct orion5x_ddr_addr_decode_registers *winregs = 23 (struct orion5x_ddr_addr_decode_registers *) 24 ORION5X_DRAM_BASE; 25 26 u32 result = 0; 27 u32 enable = 0x01 & winregs[bank].size; 28 29 if ((!enable) || (bank > BANK3)) 30 return 0; 31 32 result = winregs[bank].base; 33 return result; 34 } 35 int dram_init (void) 36 { 37 /* dram_init must store complete ramsize in gd->ram_size */ 38 gd->ram_size = get_ram_size( 39 (long *) orion5x_sdram_bar(0), 40 CONFIG_MAX_RAM_BANK_SIZE); 41 return 0; 42 } 43 44 int dram_init_banksize(void) 45 { 46 int i; 47 48 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 49 gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); 50 gd->bd->bi_dram[i].size = get_ram_size( 51 (long *) (gd->bd->bi_dram[i].start), 52 CONFIG_MAX_RAM_BANK_SIZE); 53 } 54 55 return 0; 56 } 57