1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2983e3700STom Rini /*
3983e3700STom Rini * TI SATA platform driver
4983e3700STom Rini *
5983e3700STom Rini * (C) Copyright 2013
6983e3700STom Rini * Texas Instruments, <www.ti.com>
7983e3700STom Rini */
8983e3700STom Rini
9983e3700STom Rini #include <common.h>
10983e3700STom Rini #include <ahci.h>
11983e3700STom Rini #include <scsi.h>
12983e3700STom Rini #include <asm/arch/clock.h>
13983e3700STom Rini #include <asm/arch/sata.h>
14983e3700STom Rini #include <sata.h>
15983e3700STom Rini #include <asm/io.h>
16983e3700STom Rini #include "pipe3-phy.h"
17983e3700STom Rini
18983e3700STom Rini static struct pipe3_dpll_map dpll_map_sata[] = {
19983e3700STom Rini {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
20983e3700STom Rini {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
21983e3700STom Rini {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
22983e3700STom Rini {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
23983e3700STom Rini {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
24983e3700STom Rini {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
25983e3700STom Rini { }, /* Terminator */
26983e3700STom Rini };
27983e3700STom Rini
28983e3700STom Rini struct omap_pipe3 sata_phy = {
29983e3700STom Rini .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
30983e3700STom Rini /* .power_reg is updated at runtime */
31983e3700STom Rini .dpll_map = dpll_map_sata,
32983e3700STom Rini };
33983e3700STom Rini
init_sata(int dev)34983e3700STom Rini int init_sata(int dev)
35983e3700STom Rini {
36983e3700STom Rini int ret;
37983e3700STom Rini u32 val;
38983e3700STom Rini
39983e3700STom Rini sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
40983e3700STom Rini
41983e3700STom Rini /* Power up the PHY */
42983e3700STom Rini phy_pipe3_power_on(&sata_phy);
43983e3700STom Rini
44983e3700STom Rini /* Enable SATA module, No Idle, No Standby */
45983e3700STom Rini val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
46983e3700STom Rini writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
47983e3700STom Rini
48983e3700STom Rini ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
49983e3700STom Rini
50983e3700STom Rini return ret;
51983e3700STom Rini }
52983e3700STom Rini
reset_sata(int dev)53983e3700STom Rini int reset_sata(int dev)
54983e3700STom Rini {
55983e3700STom Rini return 0;
56983e3700STom Rini }
57983e3700STom Rini
58983e3700STom Rini /* On OMAP platforms SATA provides the SCSI subsystem */
scsi_init(void)59983e3700STom Rini void scsi_init(void)
60983e3700STom Rini {
61983e3700STom Rini init_sata(0);
62983e3700STom Rini scsi_scan(1);
63983e3700STom Rini }
64983e3700STom Rini
scsi_bus_reset(struct udevice * dev)654682c8a1SSimon Glass int scsi_bus_reset(struct udevice *dev)
66983e3700STom Rini {
67983e3700STom Rini ahci_reset((void __iomem *)DWC_AHSATA_BASE);
68983e3700STom Rini ahci_init((void __iomem *)DWC_AHSATA_BASE);
694682c8a1SSimon Glass
704682c8a1SSimon Glass return 0;
71983e3700STom Rini }
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