1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *
4  * HW regs data for OMAP5 Soc
5  *
6  * (C) Copyright 2013
7  * Texas Instruments, <www.ti.com>
8  *
9  * Sricharan R <r.sricharan@ti.com>
10  */
11 
12 #include <asm/omap_common.h>
13 #include <asm/io.h>
14 
15 struct prcm_regs const omap5_es1_prcm = {
16 	/* cm1.ckgen */
17 	.cm_clksel_core = 0x4a004100,
18 	.cm_clksel_abe = 0x4a004108,
19 	.cm_dll_ctrl = 0x4a004110,
20 	.cm_clkmode_dpll_core = 0x4a004120,
21 	.cm_idlest_dpll_core = 0x4a004124,
22 	.cm_autoidle_dpll_core = 0x4a004128,
23 	.cm_clksel_dpll_core = 0x4a00412c,
24 	.cm_div_m2_dpll_core = 0x4a004130,
25 	.cm_div_m3_dpll_core = 0x4a004134,
26 	.cm_div_h11_dpll_core = 0x4a004138,
27 	.cm_div_h12_dpll_core = 0x4a00413c,
28 	.cm_div_h13_dpll_core = 0x4a004140,
29 	.cm_div_h14_dpll_core = 0x4a004144,
30 	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
31 	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
32 	.cm_emu_override_dpll_core = 0x4a004150,
33 	.cm_div_h22_dpllcore = 0x4a004154,
34 	.cm_div_h23_dpll_core = 0x4a004158,
35 	.cm_clkmode_dpll_mpu = 0x4a004160,
36 	.cm_idlest_dpll_mpu = 0x4a004164,
37 	.cm_autoidle_dpll_mpu = 0x4a004168,
38 	.cm_clksel_dpll_mpu = 0x4a00416c,
39 	.cm_div_m2_dpll_mpu = 0x4a004170,
40 	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
41 	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
42 	.cm_bypclk_dpll_mpu = 0x4a00419c,
43 	.cm_clkmode_dpll_iva = 0x4a0041a0,
44 	.cm_idlest_dpll_iva = 0x4a0041a4,
45 	.cm_autoidle_dpll_iva = 0x4a0041a8,
46 	.cm_clksel_dpll_iva = 0x4a0041ac,
47 	.cm_div_h11_dpll_iva = 0x4a0041b8,
48 	.cm_div_h12_dpll_iva = 0x4a0041bc,
49 	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
50 	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
51 	.cm_bypclk_dpll_iva = 0x4a0041dc,
52 	.cm_clkmode_dpll_abe = 0x4a0041e0,
53 	.cm_idlest_dpll_abe = 0x4a0041e4,
54 	.cm_autoidle_dpll_abe = 0x4a0041e8,
55 	.cm_clksel_dpll_abe = 0x4a0041ec,
56 	.cm_div_m2_dpll_abe = 0x4a0041f0,
57 	.cm_div_m3_dpll_abe = 0x4a0041f4,
58 	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
59 	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
60 	.cm_clkmode_dpll_ddrphy = 0x4a004220,
61 	.cm_idlest_dpll_ddrphy = 0x4a004224,
62 	.cm_autoidle_dpll_ddrphy = 0x4a004228,
63 	.cm_clksel_dpll_ddrphy = 0x4a00422c,
64 	.cm_div_m2_dpll_ddrphy = 0x4a004230,
65 	.cm_div_h11_dpll_ddrphy = 0x4a004238,
66 	.cm_div_h12_dpll_ddrphy = 0x4a00423c,
67 	.cm_div_h13_dpll_ddrphy = 0x4a004240,
68 	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
69 	.cm_shadow_freq_config1 = 0x4a004260,
70 	.cm_mpu_mpu_clkctrl = 0x4a004320,
71 
72 	/* cm1.dsp */
73 	.cm_dsp_clkstctrl = 0x4a004400,
74 	.cm_dsp_dsp_clkctrl = 0x4a004420,
75 
76 	/* cm1.abe */
77 	.cm1_abe_clkstctrl = 0x4a004500,
78 	.cm1_abe_l4abe_clkctrl = 0x4a004520,
79 	.cm1_abe_aess_clkctrl = 0x4a004528,
80 	.cm1_abe_pdm_clkctrl = 0x4a004530,
81 	.cm1_abe_dmic_clkctrl = 0x4a004538,
82 	.cm1_abe_mcasp_clkctrl = 0x4a004540,
83 	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
84 	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
85 	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
86 	.cm1_abe_slimbus_clkctrl = 0x4a004560,
87 	.cm1_abe_timer5_clkctrl = 0x4a004568,
88 	.cm1_abe_timer6_clkctrl = 0x4a004570,
89 	.cm1_abe_timer7_clkctrl = 0x4a004578,
90 	.cm1_abe_timer8_clkctrl = 0x4a004580,
91 	.cm1_abe_wdt3_clkctrl = 0x4a004588,
92 
93 	/* cm2.ckgen */
94 	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
95 	.cm_clksel_usb_60mhz = 0x4a008104,
96 	.cm_scale_fclk = 0x4a008108,
97 	.cm_core_dvfs_perf1 = 0x4a008110,
98 	.cm_core_dvfs_perf2 = 0x4a008114,
99 	.cm_core_dvfs_perf3 = 0x4a008118,
100 	.cm_core_dvfs_perf4 = 0x4a00811c,
101 	.cm_core_dvfs_current = 0x4a008124,
102 	.cm_iva_dvfs_perf_tesla = 0x4a008128,
103 	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
104 	.cm_iva_dvfs_perf_abe = 0x4a008130,
105 	.cm_iva_dvfs_current = 0x4a008138,
106 	.cm_clkmode_dpll_per = 0x4a008140,
107 	.cm_idlest_dpll_per = 0x4a008144,
108 	.cm_autoidle_dpll_per = 0x4a008148,
109 	.cm_clksel_dpll_per = 0x4a00814c,
110 	.cm_div_m2_dpll_per = 0x4a008150,
111 	.cm_div_m3_dpll_per = 0x4a008154,
112 	.cm_div_h11_dpll_per = 0x4a008158,
113 	.cm_div_h12_dpll_per = 0x4a00815c,
114 	.cm_div_h14_dpll_per = 0x4a008164,
115 	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
116 	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
117 	.cm_emu_override_dpll_per = 0x4a008170,
118 	.cm_clkmode_dpll_usb = 0x4a008180,
119 	.cm_idlest_dpll_usb = 0x4a008184,
120 	.cm_autoidle_dpll_usb = 0x4a008188,
121 	.cm_clksel_dpll_usb = 0x4a00818c,
122 	.cm_div_m2_dpll_usb = 0x4a008190,
123 	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
124 	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
125 	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
126 	.cm_clkmode_dpll_unipro = 0x4a0081c0,
127 	.cm_idlest_dpll_unipro = 0x4a0081c4,
128 	.cm_autoidle_dpll_unipro = 0x4a0081c8,
129 	.cm_clksel_dpll_unipro = 0x4a0081cc,
130 	.cm_div_m2_dpll_unipro = 0x4a0081d0,
131 	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
132 	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
133 
134 	/* cm2.core */
135 	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
136 	.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
137 	.cm_l3_1_clkstctrl = 0x4a008700,
138 	.cm_l3_1_dynamicdep = 0x4a008708,
139 	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
140 	.cm_l3_2_clkstctrl = 0x4a008800,
141 	.cm_l3_2_dynamicdep = 0x4a008808,
142 	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
143 	.cm_l3_gpmc_clkctrl = 0x4a008828,
144 	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
145 	.cm_mpu_m3_clkstctrl = 0x4a008900,
146 	.cm_mpu_m3_staticdep = 0x4a008904,
147 	.cm_mpu_m3_dynamicdep = 0x4a008908,
148 	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
149 	.cm_sdma_clkstctrl = 0x4a008a00,
150 	.cm_sdma_staticdep = 0x4a008a04,
151 	.cm_sdma_dynamicdep = 0x4a008a08,
152 	.cm_sdma_sdma_clkctrl = 0x4a008a20,
153 	.cm_memif_clkstctrl = 0x4a008b00,
154 	.cm_memif_dmm_clkctrl = 0x4a008b20,
155 	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
156 	.cm_memif_emif_1_clkctrl = 0x4a008b30,
157 	.cm_memif_emif_2_clkctrl = 0x4a008b38,
158 	.cm_memif_dll_clkctrl = 0x4a008b40,
159 	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
160 	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
161 	.cm_memif_dll_h_clkctrl = 0x4a008b60,
162 	.cm_c2c_clkstctrl = 0x4a008c00,
163 	.cm_c2c_staticdep = 0x4a008c04,
164 	.cm_c2c_dynamicdep = 0x4a008c08,
165 	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
166 	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
167 	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
168 	.cm_l4cfg_clkstctrl = 0x4a008d00,
169 	.cm_l4cfg_dynamicdep = 0x4a008d08,
170 	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
171 	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
172 	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
173 	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
174 	.cm_l3instr_clkstctrl = 0x4a008e00,
175 	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
176 	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
177 	.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
178 
179 	/* cm2.ivahd */
180 	.cm_ivahd_clkstctrl = 0x4a008f00,
181 	.cm_ivahd_ivahd_clkctrl = 0x4a008f20,
182 	.cm_ivahd_sl2_clkctrl = 0x4a008f28,
183 
184 	/* cm2.cam */
185 	.cm_cam_clkstctrl = 0x4a009000,
186 	.cm_cam_iss_clkctrl = 0x4a009020,
187 	.cm_cam_fdif_clkctrl = 0x4a009028,
188 
189 	/* cm2.dss */
190 	.cm_dss_clkstctrl = 0x4a009100,
191 	.cm_dss_dss_clkctrl = 0x4a009120,
192 
193 	/* cm2.sgx */
194 	.cm_sgx_clkstctrl = 0x4a009200,
195 	.cm_sgx_sgx_clkctrl = 0x4a009220,
196 
197 	/* cm2.l3init */
198 	.cm_l3init_clkstctrl = 0x4a009300,
199 	.cm_l3init_hsmmc1_clkctrl = 0x4a009328,
200 	.cm_l3init_hsmmc2_clkctrl = 0x4a009330,
201 	.cm_l3init_hsi_clkctrl = 0x4a009338,
202 	.cm_l3init_hsusbhost_clkctrl = 0x4a009358,
203 	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
204 	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
205 	.cm_l3init_p1500_clkctrl = 0x4a009378,
206 	.cm_l3init_sata_clkctrl = 0x4a009388,
207 	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
208 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
209 	.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
210 
211 	/* cm2.l4per */
212 	.cm_l4per_clkstctrl = 0x4a009400,
213 	.cm_l4per_dynamicdep = 0x4a009408,
214 	.cm_l4per_adc_clkctrl = 0x4a009420,
215 	.cm_l4per_gptimer10_clkctrl = 0x4a009428,
216 	.cm_l4per_gptimer11_clkctrl = 0x4a009430,
217 	.cm_l4per_gptimer2_clkctrl = 0x4a009438,
218 	.cm_l4per_gptimer3_clkctrl = 0x4a009440,
219 	.cm_l4per_gptimer4_clkctrl = 0x4a009448,
220 	.cm_l4per_gptimer9_clkctrl = 0x4a009450,
221 	.cm_l4per_elm_clkctrl = 0x4a009458,
222 	.cm_l4per_gpio2_clkctrl = 0x4a009460,
223 	.cm_l4per_gpio3_clkctrl = 0x4a009468,
224 	.cm_l4per_gpio4_clkctrl = 0x4a009470,
225 	.cm_l4per_gpio5_clkctrl = 0x4a009478,
226 	.cm_l4per_gpio6_clkctrl = 0x4a009480,
227 	.cm_l4per_hdq1w_clkctrl = 0x4a009488,
228 	.cm_l4per_hecc1_clkctrl = 0x4a009490,
229 	.cm_l4per_hecc2_clkctrl = 0x4a009498,
230 	.cm_l4per_i2c1_clkctrl = 0x4a0094a0,
231 	.cm_l4per_i2c2_clkctrl = 0x4a0094a8,
232 	.cm_l4per_i2c3_clkctrl = 0x4a0094b0,
233 	.cm_l4per_i2c4_clkctrl = 0x4a0094b8,
234 	.cm_l4per_l4per_clkctrl = 0x4a0094c0,
235 	.cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
236 	.cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
237 	.cm_l4per_mgate_clkctrl = 0x4a0094e8,
238 	.cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
239 	.cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
240 	.cm_l4per_mcspi3_clkctrl = 0x4a009500,
241 	.cm_l4per_mcspi4_clkctrl = 0x4a009508,
242 	.cm_l4per_gpio7_clkctrl = 0x4a009510,
243 	.cm_l4per_gpio8_clkctrl = 0x4a009518,
244 	.cm_l4per_mmcsd3_clkctrl = 0x4a009520,
245 	.cm_l4per_mmcsd4_clkctrl = 0x4a009528,
246 	.cm_l4per_msprohg_clkctrl = 0x4a009530,
247 	.cm_l4per_slimbus2_clkctrl = 0x4a009538,
248 	.cm_l4per_uart1_clkctrl = 0x4a009540,
249 	.cm_l4per_uart2_clkctrl = 0x4a009548,
250 	.cm_l4per_uart3_clkctrl = 0x4a009550,
251 	.cm_l4per_uart4_clkctrl = 0x4a009558,
252 	.cm_l4per_mmcsd5_clkctrl = 0x4a009560,
253 	.cm_l4per_i2c5_clkctrl = 0x4a009568,
254 	.cm_l4per_uart5_clkctrl = 0x4a009570,
255 	.cm_l4per_uart6_clkctrl = 0x4a009578,
256 	.cm_l4sec_clkstctrl = 0x4a009580,
257 	.cm_l4sec_staticdep = 0x4a009584,
258 	.cm_l4sec_dynamicdep = 0x4a009588,
259 	.cm_l4sec_aes1_clkctrl = 0x4a0095a0,
260 	.cm_l4sec_aes2_clkctrl = 0x4a0095a8,
261 	.cm_l4sec_des3des_clkctrl = 0x4a0095b0,
262 	.cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
263 	.cm_l4sec_rng_clkctrl = 0x4a0095c0,
264 	.cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
265 	.cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
266 
267 	/* l4 wkup regs */
268 	.cm_abe_pll_ref_clksel = 0x4ae0610c,
269 	.cm_sys_clksel = 0x4ae06110,
270 	.cm_wkup_clkstctrl = 0x4ae07800,
271 	.cm_wkup_l4wkup_clkctrl = 0x4ae07820,
272 	.cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
273 	.cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
274 	.cm_wkup_gpio1_clkctrl = 0x4ae07838,
275 	.cm_wkup_gptimer1_clkctrl = 0x4ae07840,
276 	.cm_wkup_gptimer12_clkctrl = 0x4ae07848,
277 	.cm_wkup_synctimer_clkctrl = 0x4ae07850,
278 	.cm_wkup_usim_clkctrl = 0x4ae07858,
279 	.cm_wkup_sarram_clkctrl = 0x4ae07860,
280 	.cm_wkup_keyboard_clkctrl = 0x4ae07878,
281 	.cm_wkup_rtc_clkctrl = 0x4ae07880,
282 	.cm_wkup_bandgap_clkctrl = 0x4ae07888,
283 	.cm_wkupaon_scrm_clkctrl = 0x4ae07890,
284 	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
285 	.prm_rstctrl = 0x4ae07b00,
286 	.prm_rstst = 0x4ae07b04,
287 	.prm_rsttime = 0x4ae07b08,
288 	.prm_vc_val_bypass = 0x4ae07ba0,
289 	.prm_vc_cfg_i2c_mode = 0x4ae07bb4,
290 	.prm_vc_cfg_i2c_clk = 0x4ae07bb8,
291 
292 	/* SCRM stuff, used by some boards */
293 	.scrm_auxclk0 = 0x4ae0a310,
294 	.scrm_auxclk1 = 0x4ae0a314,
295 };
296 
297 struct omap_sys_ctrl_regs const omap5_ctrl = {
298 	.control_status				= 0x4A002134,
299 	.control_std_fuse_die_id_0		= 0x4A002200,
300 	.control_std_fuse_die_id_1		= 0x4A002208,
301 	.control_std_fuse_die_id_2		= 0x4A00220C,
302 	.control_std_fuse_die_id_3		= 0x4A002210,
303 	.control_phy_power_usb 			= 0x4A002370,
304 	.control_phy_power_sata			= 0x4A002374,
305 	.control_padconf_core_base		= 0x4A002800,
306 	.control_paconf_global			= 0x4A002DA0,
307 	.control_paconf_mode			= 0x4A002DA4,
308 	.control_smart1io_padconf_0		= 0x4A002DA8,
309 	.control_smart1io_padconf_1		= 0x4A002DAC,
310 	.control_smart1io_padconf_2		= 0x4A002DB0,
311 	.control_smart2io_padconf_0		= 0x4A002DB4,
312 	.control_smart2io_padconf_1		= 0x4A002DB8,
313 	.control_smart2io_padconf_2		= 0x4A002DBC,
314 	.control_smart3io_padconf_0		= 0x4A002DC0,
315 	.control_smart3io_padconf_1		= 0x4A002DC4,
316 	.control_pbias				= 0x4A002E00,
317 	.control_i2c_0				= 0x4A002E04,
318 	.control_camera_rx			= 0x4A002E08,
319 	.control_hdmi_tx_phy			= 0x4A002E0C,
320 	.control_uniportm			= 0x4A002E10,
321 	.control_dsiphy				= 0x4A002E14,
322 	.control_mcbsplp			= 0x4A002E18,
323 	.control_usb2phycore			= 0x4A002E1C,
324 	.control_hdmi_1				= 0x4A002E20,
325 	.control_hsi				= 0x4A002E24,
326 	.control_ddr3ch1_0			= 0x4A002E30,
327 	.control_ddr3ch2_0			= 0x4A002E34,
328 	.control_ddrch1_0			= 0x4A002E38,
329 	.control_ddrch1_1			= 0x4A002E3C,
330 	.control_ddrch2_0			= 0x4A002E40,
331 	.control_ddrch2_1			= 0x4A002E44,
332 	.control_lpddr2ch1_0			= 0x4A002E48,
333 	.control_lpddr2ch1_1			= 0x4A002E4C,
334 	.control_ddrio_0			= 0x4A002E50,
335 	.control_ddrio_1			= 0x4A002E54,
336 	.control_ddrio_2			= 0x4A002E58,
337 	.control_hyst_1				= 0x4A002E5C,
338 	.control_usbb_hsic_control		= 0x4A002E60,
339 	.control_c2c				= 0x4A002E64,
340 	.control_core_control_spare_rw		= 0x4A002E68,
341 	.control_core_control_spare_r		= 0x4A002E6C,
342 	.control_core_control_spare_r_c0	= 0x4A002E70,
343 	.control_srcomp_north_side		= 0x4A002E74,
344 	.control_srcomp_south_side		= 0x4A002E78,
345 	.control_srcomp_east_side		= 0x4A002E7C,
346 	.control_srcomp_west_side		= 0x4A002E80,
347 	.control_srcomp_code_latch		= 0x4A002E84,
348 	.control_port_emif1_sdram_config	= 0x4AE0C110,
349 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
350 	.control_port_emif2_sdram_config	= 0x4AE0C118,
351 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
352 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
353 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C318,
354 	.control_wkup_ldovbb_mm_voltage_ctrl	= 0x4AE0C314,
355 	.control_padconf_wkup_base		= 0x4AE0C800,
356 	.control_smart1nopmio_padconf_0		= 0x4AE0CDA0,
357 	.control_smart1nopmio_padconf_1		= 0x4AE0CDA4,
358 	.control_padconf_mode			= 0x4AE0CDA8,
359 	.control_xtal_oscillator		= 0x4AE0CDAC,
360 	.control_i2c_2				= 0x4AE0CDB0,
361 	.control_ckobuffer			= 0x4AE0CDB4,
362 	.control_wkup_control_spare_rw		= 0x4AE0CDB8,
363 	.control_wkup_control_spare_r		= 0x4AE0CDBC,
364 	.control_wkup_control_spare_r_c0	= 0x4AE0CDC0,
365 	.control_srcomp_east_side_wkup		= 0x4AE0CDC4,
366 	.control_efuse_1			= 0x4AE0CDC8,
367 	.control_efuse_2			= 0x4AE0CDCC,
368 	.control_efuse_3			= 0x4AE0CDD0,
369 	.control_efuse_4			= 0x4AE0CDD4,
370 	.control_efuse_5			= 0x4AE0CDD8,
371 	.control_efuse_6			= 0x4AE0CDDC,
372 	.control_efuse_7			= 0x4AE0CDE0,
373 	.control_efuse_8			= 0x4AE0CDE4,
374 	.control_efuse_9			= 0x4AE0CDE8,
375 	.control_efuse_10			= 0x4AE0CDEC,
376 	.control_efuse_11			= 0x4AE0CDF0,
377 	.control_efuse_12			= 0x4AE0CDF4,
378 	.control_efuse_13			= 0x4AE0CDF8,
379 };
380 
381 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
382 	.control_status				= 0x4A002134,
383 	.control_phy_power_usb			= 0x4A002370,
384 	.control_phy_power_sata			= 0x4A002374,
385 	.ctrl_core_sma_sw_0			= 0x4A0023FC,
386 	.ctrl_core_sma_sw_1			= 0x4A002534,
387 	.control_core_mac_id_0_lo		= 0x4A002514,
388 	.control_core_mac_id_0_hi		= 0x4A002518,
389 	.control_core_mac_id_1_lo		= 0x4A00251C,
390 	.control_core_mac_id_1_hi		= 0x4A002520,
391 	.control_core_mmr_lock1			= 0x4A002540,
392 	.control_core_mmr_lock2			= 0x4A002544,
393 	.control_core_mmr_lock3			= 0x4A002548,
394 	.control_core_mmr_lock4			= 0x4A00254C,
395 	.control_core_mmr_lock5			= 0x4A002550,
396 	.control_core_control_io1		= 0x4A002554,
397 	.control_core_control_io2		= 0x4A002558,
398 	.control_paconf_global			= 0x4A002DA0,
399 	.control_paconf_mode			= 0x4A002DA4,
400 	.control_smart1io_padconf_0		= 0x4A002DA8,
401 	.control_smart1io_padconf_1		= 0x4A002DAC,
402 	.control_smart1io_padconf_2		= 0x4A002DB0,
403 	.control_smart2io_padconf_0		= 0x4A002DB4,
404 	.control_smart2io_padconf_1		= 0x4A002DB8,
405 	.control_smart2io_padconf_2		= 0x4A002DBC,
406 	.control_smart3io_padconf_0		= 0x4A002DC0,
407 	.control_smart3io_padconf_1		= 0x4A002DC4,
408 	.control_pbias				= 0x4A002E00,
409 	.control_i2c_0				= 0x4A002E04,
410 	.control_camera_rx			= 0x4A002E08,
411 	.control_hdmi_tx_phy			= 0x4A002E0C,
412 	.control_uniportm			= 0x4A002E10,
413 	.control_dsiphy				= 0x4A002E14,
414 	.control_mcbsplp			= 0x4A002E18,
415 	.control_usb2phycore			= 0x4A002E1C,
416 	.control_hdmi_1				= 0x4A002E20,
417 	.control_hsi				= 0x4A002E24,
418 	.control_ddr3ch1_0			= 0x4A002E30,
419 	.control_ddr3ch2_0			= 0x4A002E34,
420 	.control_ddrch1_0			= 0x4A002E38,
421 	.control_ddrch1_1			= 0x4A002E3C,
422 	.control_ddrch2_0			= 0x4A002E40,
423 	.control_ddrch2_1			= 0x4A002E44,
424 	.control_lpddr2ch1_0			= 0x4A002E48,
425 	.control_lpddr2ch1_1			= 0x4A002E4C,
426 	.control_ddrio_0			= 0x4A002E50,
427 	.control_ddrio_1			= 0x4A002E54,
428 	.control_ddrio_2			= 0x4A002E58,
429 	.control_hyst_1				= 0x4A002E5C,
430 	.control_usbb_hsic_control		= 0x4A002E60,
431 	.control_c2c				= 0x4A002E64,
432 	.control_core_control_spare_rw		= 0x4A002E68,
433 	.control_core_control_spare_r		= 0x4A002E6C,
434 	.control_core_control_spare_r_c0	= 0x4A002E70,
435 	.control_srcomp_north_side		= 0x4A002E74,
436 	.control_srcomp_south_side		= 0x4A002E78,
437 	.control_srcomp_east_side		= 0x4A002E7C,
438 	.control_srcomp_west_side		= 0x4A002E80,
439 	.control_srcomp_code_latch		= 0x4A002E84,
440 	.control_ddr_control_ext_0		= 0x4A002E88,
441 	.control_padconf_core_base		= 0x4A003400,
442 	.control_port_emif1_sdram_config	= 0x4AE0C110,
443 	.control_port_emif1_lpddr2_nvm_config	= 0x4AE0C114,
444 	.control_port_emif2_sdram_config	= 0x4AE0C118,
445 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
446 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
447 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
448 	.control_wkup_ldovbb_iva_voltage_ctrl	= 0x4A002470,
449 	.control_wkup_ldovbb_eve_voltage_ctrl	= 0x4A00246C,
450 	.control_wkup_ldovbb_gpu_voltage_ctrl	= 0x4AE0C154,
451 	.control_std_fuse_die_id_0		= 0x4AE0C200,
452 	.control_std_fuse_die_id_1		= 0x4AE0C208,
453 	.control_std_fuse_die_id_2		= 0x4AE0C20C,
454 	.control_std_fuse_die_id_3		= 0x4AE0C210,
455 	.control_padconf_mode			= 0x4AE0C5A0,
456 	.control_xtal_oscillator		= 0x4AE0C5A4,
457 	.control_i2c_2				= 0x4AE0C5A8,
458 	.control_ckobuffer			= 0x4AE0C5AC,
459 	.control_wkup_control_spare_rw		= 0x4AE0C5B0,
460 	.control_wkup_control_spare_r		= 0x4AE0C5B4,
461 	.control_wkup_control_spare_r_c0	= 0x4AE0C5B8,
462 	.control_srcomp_east_side_wkup		= 0x4AE0C5BC,
463 	.control_efuse_1			= 0x4AE0C5C8,
464 	.control_efuse_2			= 0x4AE0C5CC,
465 	.control_efuse_3			= 0x4AE0C5D0,
466 	.control_efuse_4			= 0x4AE0C5D4,
467 	.control_efuse_13			= 0x4AE0C5F0,
468 	.iodelay_config_base			= 0x4844A000,
469 };
470 
471 struct prcm_regs const omap5_es2_prcm = {
472 	/* cm1.ckgen */
473 	.cm_clksel_core = 0x4a004100,
474 	.cm_clksel_abe = 0x4a004108,
475 	.cm_dll_ctrl = 0x4a004110,
476 	.cm_clkmode_dpll_core = 0x4a004120,
477 	.cm_idlest_dpll_core = 0x4a004124,
478 	.cm_autoidle_dpll_core = 0x4a004128,
479 	.cm_clksel_dpll_core = 0x4a00412c,
480 	.cm_div_m2_dpll_core = 0x4a004130,
481 	.cm_div_m3_dpll_core = 0x4a004134,
482 	.cm_div_h11_dpll_core = 0x4a004138,
483 	.cm_div_h12_dpll_core = 0x4a00413c,
484 	.cm_div_h13_dpll_core = 0x4a004140,
485 	.cm_div_h14_dpll_core = 0x4a004144,
486 	.cm_ssc_deltamstep_dpll_core = 0x4a004148,
487 	.cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
488 	.cm_div_h21_dpll_core = 0x4a004150,
489 	.cm_div_h22_dpllcore = 0x4a004154,
490 	.cm_div_h23_dpll_core = 0x4a004158,
491 	.cm_div_h24_dpll_core = 0x4a00415c,
492 	.cm_clkmode_dpll_mpu = 0x4a004160,
493 	.cm_idlest_dpll_mpu = 0x4a004164,
494 	.cm_autoidle_dpll_mpu = 0x4a004168,
495 	.cm_clksel_dpll_mpu = 0x4a00416c,
496 	.cm_div_m2_dpll_mpu = 0x4a004170,
497 	.cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
498 	.cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
499 	.cm_bypclk_dpll_mpu = 0x4a00419c,
500 	.cm_clkmode_dpll_iva = 0x4a0041a0,
501 	.cm_idlest_dpll_iva = 0x4a0041a4,
502 	.cm_autoidle_dpll_iva = 0x4a0041a8,
503 	.cm_clksel_dpll_iva = 0x4a0041ac,
504 	.cm_div_h11_dpll_iva = 0x4a0041b8,
505 	.cm_div_h12_dpll_iva = 0x4a0041bc,
506 	.cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
507 	.cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
508 	.cm_bypclk_dpll_iva = 0x4a0041dc,
509 	.cm_clkmode_dpll_abe = 0x4a0041e0,
510 	.cm_idlest_dpll_abe = 0x4a0041e4,
511 	.cm_autoidle_dpll_abe = 0x4a0041e8,
512 	.cm_clksel_dpll_abe = 0x4a0041ec,
513 	.cm_div_m2_dpll_abe = 0x4a0041f0,
514 	.cm_div_m3_dpll_abe = 0x4a0041f4,
515 	.cm_ssc_deltamstep_dpll_abe = 0x4a004208,
516 	.cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
517 	.cm_clkmode_dpll_ddrphy = 0x4a004220,
518 	.cm_idlest_dpll_ddrphy = 0x4a004224,
519 	.cm_autoidle_dpll_ddrphy = 0x4a004228,
520 	.cm_clksel_dpll_ddrphy = 0x4a00422c,
521 	.cm_div_m2_dpll_ddrphy = 0x4a004230,
522 	.cm_div_h11_dpll_ddrphy = 0x4a004238,
523 	.cm_div_h12_dpll_ddrphy = 0x4a00423c,
524 	.cm_div_h13_dpll_ddrphy = 0x4a004240,
525 	.cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
526 	.cm_shadow_freq_config1 = 0x4a004260,
527 	.cm_mpu_mpu_clkctrl = 0x4a004320,
528 
529 	/* cm1.dsp */
530 	.cm_dsp_clkstctrl = 0x4a004400,
531 	.cm_dsp_dsp_clkctrl = 0x4a004420,
532 
533 	/* cm1.abe */
534 	.cm1_abe_clkstctrl = 0x4a004500,
535 	.cm1_abe_l4abe_clkctrl = 0x4a004520,
536 	.cm1_abe_aess_clkctrl = 0x4a004528,
537 	.cm1_abe_pdm_clkctrl = 0x4a004530,
538 	.cm1_abe_dmic_clkctrl = 0x4a004538,
539 	.cm1_abe_mcasp_clkctrl = 0x4a004540,
540 	.cm1_abe_mcbsp1_clkctrl = 0x4a004548,
541 	.cm1_abe_mcbsp2_clkctrl = 0x4a004550,
542 	.cm1_abe_mcbsp3_clkctrl = 0x4a004558,
543 	.cm1_abe_slimbus_clkctrl = 0x4a004560,
544 	.cm1_abe_timer5_clkctrl = 0x4a004568,
545 	.cm1_abe_timer6_clkctrl = 0x4a004570,
546 	.cm1_abe_timer7_clkctrl = 0x4a004578,
547 	.cm1_abe_timer8_clkctrl = 0x4a004580,
548 	.cm1_abe_wdt3_clkctrl = 0x4a004588,
549 
550 	/* cm2.ckgen */
551 	.cm_clksel_mpu_m3_iss_root = 0x4a008100,
552 	.cm_clksel_usb_60mhz = 0x4a008104,
553 	.cm_scale_fclk = 0x4a008108,
554 	.cm_core_dvfs_perf1 = 0x4a008110,
555 	.cm_core_dvfs_perf2 = 0x4a008114,
556 	.cm_core_dvfs_perf3 = 0x4a008118,
557 	.cm_core_dvfs_perf4 = 0x4a00811c,
558 	.cm_core_dvfs_current = 0x4a008124,
559 	.cm_iva_dvfs_perf_tesla = 0x4a008128,
560 	.cm_iva_dvfs_perf_ivahd = 0x4a00812c,
561 	.cm_iva_dvfs_perf_abe = 0x4a008130,
562 	.cm_iva_dvfs_current = 0x4a008138,
563 	.cm_clkmode_dpll_per = 0x4a008140,
564 	.cm_idlest_dpll_per = 0x4a008144,
565 	.cm_autoidle_dpll_per = 0x4a008148,
566 	.cm_clksel_dpll_per = 0x4a00814c,
567 	.cm_div_m2_dpll_per = 0x4a008150,
568 	.cm_div_m3_dpll_per = 0x4a008154,
569 	.cm_div_h11_dpll_per = 0x4a008158,
570 	.cm_div_h12_dpll_per = 0x4a00815c,
571 	.cm_div_h13_dpll_per = 0x4a008160,
572 	.cm_div_h14_dpll_per = 0x4a008164,
573 	.cm_ssc_deltamstep_dpll_per = 0x4a008168,
574 	.cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
575 	.cm_emu_override_dpll_per = 0x4a008170,
576 	.cm_clkmode_dpll_usb = 0x4a008180,
577 	.cm_idlest_dpll_usb = 0x4a008184,
578 	.cm_autoidle_dpll_usb = 0x4a008188,
579 	.cm_clksel_dpll_usb = 0x4a00818c,
580 	.cm_div_m2_dpll_usb = 0x4a008190,
581 	.cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
582 	.cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
583 	.cm_clkdcoldo_dpll_usb = 0x4a0081b4,
584 	.cm_clkmode_dpll_unipro = 0x4a0081c0,
585 	.cm_idlest_dpll_unipro = 0x4a0081c4,
586 	.cm_autoidle_dpll_unipro = 0x4a0081c8,
587 	.cm_clksel_dpll_unipro = 0x4a0081cc,
588 	.cm_div_m2_dpll_unipro = 0x4a0081d0,
589 	.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
590 	.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
591 	.cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640,
592 	.cm_coreaon_bandgap_clkctrl = 0x4a008648,
593 	.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
594 
595 	/* cm2.core */
596 	.cm_l3_1_clkstctrl = 0x4a008700,
597 	.cm_l3_1_dynamicdep = 0x4a008708,
598 	.cm_l3_1_l3_1_clkctrl = 0x4a008720,
599 	.cm_l3_2_clkstctrl = 0x4a008800,
600 	.cm_l3_2_dynamicdep = 0x4a008808,
601 	.cm_l3_2_l3_2_clkctrl = 0x4a008820,
602 	.cm_l3_gpmc_clkctrl = 0x4a008828,
603 	.cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
604 	.cm_mpu_m3_clkstctrl = 0x4a008900,
605 	.cm_mpu_m3_staticdep = 0x4a008904,
606 	.cm_mpu_m3_dynamicdep = 0x4a008908,
607 	.cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
608 	.cm_sdma_clkstctrl = 0x4a008a00,
609 	.cm_sdma_staticdep = 0x4a008a04,
610 	.cm_sdma_dynamicdep = 0x4a008a08,
611 	.cm_sdma_sdma_clkctrl = 0x4a008a20,
612 	.cm_memif_clkstctrl = 0x4a008b00,
613 	.cm_memif_dmm_clkctrl = 0x4a008b20,
614 	.cm_memif_emif_fw_clkctrl = 0x4a008b28,
615 	.cm_memif_emif_1_clkctrl = 0x4a008b30,
616 	.cm_memif_emif_2_clkctrl = 0x4a008b38,
617 	.cm_memif_dll_clkctrl = 0x4a008b40,
618 	.cm_memif_emif_h1_clkctrl = 0x4a008b50,
619 	.cm_memif_emif_h2_clkctrl = 0x4a008b58,
620 	.cm_memif_dll_h_clkctrl = 0x4a008b60,
621 	.cm_c2c_clkstctrl = 0x4a008c00,
622 	.cm_c2c_staticdep = 0x4a008c04,
623 	.cm_c2c_dynamicdep = 0x4a008c08,
624 	.cm_c2c_sad2d_clkctrl = 0x4a008c20,
625 	.cm_c2c_modem_icr_clkctrl = 0x4a008c28,
626 	.cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
627 	.cm_l4cfg_clkstctrl = 0x4a008d00,
628 	.cm_l4cfg_dynamicdep = 0x4a008d08,
629 	.cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
630 	.cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
631 	.cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
632 	.cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
633 	.cm_l3instr_clkstctrl = 0x4a008e00,
634 	.cm_l3instr_l3_3_clkctrl = 0x4a008e20,
635 	.cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
636 	.cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
637 	.cm_l4per_clkstctrl = 0x4a009000,
638 	.cm_l4per_dynamicdep = 0x4a009008,
639 	.cm_l4per_adc_clkctrl = 0x4a009020,
640 	.cm_l4per_gptimer10_clkctrl = 0x4a009028,
641 	.cm_l4per_gptimer11_clkctrl = 0x4a009030,
642 	.cm_l4per_gptimer2_clkctrl = 0x4a009038,
643 	.cm_l4per_gptimer3_clkctrl = 0x4a009040,
644 	.cm_l4per_gptimer4_clkctrl = 0x4a009048,
645 	.cm_l4per_gptimer9_clkctrl = 0x4a009050,
646 	.cm_l4per_elm_clkctrl = 0x4a009058,
647 	.cm_l4per_gpio2_clkctrl = 0x4a009060,
648 	.cm_l4per_gpio3_clkctrl = 0x4a009068,
649 	.cm_l4per_gpio4_clkctrl = 0x4a009070,
650 	.cm_l4per_gpio5_clkctrl = 0x4a009078,
651 	.cm_l4per_gpio6_clkctrl = 0x4a009080,
652 	.cm_l4per_hdq1w_clkctrl = 0x4a009088,
653 	.cm_l4per_hecc1_clkctrl = 0x4a009090,
654 	.cm_l4per_hecc2_clkctrl = 0x4a009098,
655 	.cm_l4per_i2c1_clkctrl = 0x4a0090a0,
656 	.cm_l4per_i2c2_clkctrl = 0x4a0090a8,
657 	.cm_l4per_i2c3_clkctrl = 0x4a0090b0,
658 	.cm_l4per_i2c4_clkctrl = 0x4a0090b8,
659 	.cm_l4per_l4per_clkctrl = 0x4a0090c0,
660 	.cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
661 	.cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
662 	.cm_l4per_mgate_clkctrl = 0x4a0090e8,
663 	.cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
664 	.cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
665 	.cm_l4per_mcspi3_clkctrl = 0x4a009100,
666 	.cm_l4per_mcspi4_clkctrl = 0x4a009108,
667 	.cm_l4per_gpio7_clkctrl = 0x4a009110,
668 	.cm_l4per_gpio8_clkctrl = 0x4a009118,
669 	.cm_l4per_mmcsd3_clkctrl = 0x4a009120,
670 	.cm_l4per_mmcsd4_clkctrl = 0x4a009128,
671 	.cm_l4per_msprohg_clkctrl = 0x4a009130,
672 	.cm_l4per_slimbus2_clkctrl = 0x4a009138,
673 	.cm_l4per_uart1_clkctrl = 0x4a009140,
674 	.cm_l4per_uart2_clkctrl = 0x4a009148,
675 	.cm_l4per_uart3_clkctrl = 0x4a009150,
676 	.cm_l4per_uart4_clkctrl = 0x4a009158,
677 	.cm_l4per_mmcsd5_clkctrl = 0x4a009160,
678 	.cm_l4per_i2c5_clkctrl = 0x4a009168,
679 	.cm_l4per_uart5_clkctrl = 0x4a009170,
680 	.cm_l4per_uart6_clkctrl = 0x4a009178,
681 	.cm_l4sec_clkstctrl = 0x4a009180,
682 	.cm_l4sec_staticdep = 0x4a009184,
683 	.cm_l4sec_dynamicdep = 0x4a009188,
684 	.cm_l4sec_aes1_clkctrl = 0x4a0091a0,
685 	.cm_l4sec_aes2_clkctrl = 0x4a0091a8,
686 	.cm_l4sec_des3des_clkctrl = 0x4a0091b0,
687 	.cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
688 	.cm_l4sec_rng_clkctrl = 0x4a0091c0,
689 	.cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
690 	.cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
691 
692 	/* cm2.ivahd */
693 	.cm_ivahd_clkstctrl = 0x4a009200,
694 	.cm_ivahd_ivahd_clkctrl = 0x4a009220,
695 	.cm_ivahd_sl2_clkctrl = 0x4a009228,
696 
697 	/* cm2.cam */
698 	.cm_cam_clkstctrl = 0x4a009300,
699 	.cm_cam_iss_clkctrl = 0x4a009320,
700 	.cm_cam_fdif_clkctrl = 0x4a009328,
701 
702 	/* cm2.dss */
703 	.cm_dss_clkstctrl = 0x4a009400,
704 	.cm_dss_dss_clkctrl = 0x4a009420,
705 
706 	/* cm2.sgx */
707 	.cm_sgx_clkstctrl = 0x4a009500,
708 	.cm_sgx_sgx_clkctrl = 0x4a009520,
709 
710 	/* cm2.l3init */
711 	.cm_l3init_clkstctrl = 0x4a009600,
712 
713 	/* cm2.l3init */
714 	.cm_l3init_hsmmc1_clkctrl = 0x4a009628,
715 	.cm_l3init_hsmmc2_clkctrl = 0x4a009630,
716 	.cm_l3init_hsi_clkctrl = 0x4a009638,
717 	.cm_l3init_hsusbhost_clkctrl = 0x4a009658,
718 	.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
719 	.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
720 	.cm_l3init_p1500_clkctrl = 0x4a009678,
721 	.cm_l3init_sata_clkctrl = 0x4a009688,
722 	.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
723 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
724 	.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
725 	.cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
726 
727 	/* prm irqstatus regs */
728 	.prm_irqstatus_mpu = 0x4ae06010,
729 	.prm_irqstatus_mpu_2 = 0x4ae06014,
730 
731 	/* l4 wkup regs */
732 	.cm_abe_pll_ref_clksel = 0x4ae0610c,
733 	.cm_sys_clksel = 0x4ae06110,
734 	.cm_wkup_clkstctrl = 0x4ae07900,
735 	.cm_wkup_l4wkup_clkctrl = 0x4ae07920,
736 	.cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
737 	.cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
738 	.cm_wkup_gpio1_clkctrl = 0x4ae07938,
739 	.cm_wkup_gptimer1_clkctrl = 0x4ae07940,
740 	.cm_wkup_gptimer12_clkctrl = 0x4ae07948,
741 	.cm_wkup_synctimer_clkctrl = 0x4ae07950,
742 	.cm_wkup_usim_clkctrl = 0x4ae07958,
743 	.cm_wkup_sarram_clkctrl = 0x4ae07960,
744 	.cm_wkup_keyboard_clkctrl = 0x4ae07978,
745 	.cm_wkup_rtc_clkctrl = 0x4ae07980,
746 	.cm_wkup_bandgap_clkctrl = 0x4ae07988,
747 	.cm_wkupaon_scrm_clkctrl = 0x4ae07990,
748 	.cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
749 	.prm_rstctrl = 0x4ae07c00,
750 	.prm_rstst = 0x4ae07c04,
751 	.prm_rsttime = 0x4ae07c08,
752 	.prm_vc_val_bypass = 0x4ae07ca0,
753 	.prm_vc_cfg_i2c_mode = 0x4ae07cb4,
754 	.prm_vc_cfg_i2c_clk = 0x4ae07cb8,
755 
756 	.prm_abbldo_mpu_setup = 0x4ae07cdc,
757 	.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
758 	.prm_abbldo_mm_setup = 0x4ae07ce4,
759 	.prm_abbldo_mm_ctrl = 0x4ae07ce8,
760 
761 	/* SCRM stuff, used by some boards */
762 	.scrm_auxclk0 = 0x4ae0a310,
763 	.scrm_auxclk1 = 0x4ae0a314,
764 };
765 
766 struct prcm_regs const dra7xx_prcm = {
767 	/* cm1.ckgen */
768 	.cm_clksel_core				= 0x4a005100,
769 	.cm_clksel_abe				= 0x4a005108,
770 	.cm_dll_ctrl				= 0x4a005110,
771 	.cm_clkmode_dpll_core			= 0x4a005120,
772 	.cm_idlest_dpll_core			= 0x4a005124,
773 	.cm_autoidle_dpll_core			= 0x4a005128,
774 	.cm_clksel_dpll_core			= 0x4a00512c,
775 	.cm_div_m2_dpll_core			= 0x4a005130,
776 	.cm_div_m3_dpll_core			= 0x4a005134,
777 	.cm_div_h11_dpll_core			= 0x4a005138,
778 	.cm_div_h12_dpll_core			= 0x4a00513c,
779 	.cm_div_h13_dpll_core			= 0x4a005140,
780 	.cm_div_h14_dpll_core			= 0x4a005144,
781 	.cm_ssc_deltamstep_dpll_core		= 0x4a005148,
782 	.cm_ssc_modfreqdiv_dpll_core		= 0x4a00514c,
783 	.cm_div_h21_dpll_core			= 0x4a005150,
784 	.cm_div_h22_dpllcore			= 0x4a005154,
785 	.cm_div_h23_dpll_core			= 0x4a005158,
786 	.cm_div_h24_dpll_core			= 0x4a00515c,
787 	.cm_clkmode_dpll_mpu			= 0x4a005160,
788 	.cm_idlest_dpll_mpu			= 0x4a005164,
789 	.cm_autoidle_dpll_mpu			= 0x4a005168,
790 	.cm_clksel_dpll_mpu			= 0x4a00516c,
791 	.cm_div_m2_dpll_mpu			= 0x4a005170,
792 	.cm_ssc_deltamstep_dpll_mpu		= 0x4a005188,
793 	.cm_ssc_modfreqdiv_dpll_mpu		= 0x4a00518c,
794 	.cm_bypclk_dpll_mpu			= 0x4a00519c,
795 	.cm_clkmode_dpll_iva			= 0x4a0051a0,
796 	.cm_idlest_dpll_iva			= 0x4a0051a4,
797 	.cm_autoidle_dpll_iva			= 0x4a0051a8,
798 	.cm_clksel_dpll_iva			= 0x4a0051ac,
799 	.cm_ssc_deltamstep_dpll_iva		= 0x4a0051c8,
800 	.cm_ssc_modfreqdiv_dpll_iva		= 0x4a0051cc,
801 	.cm_bypclk_dpll_iva			= 0x4a0051dc,
802 	.cm_clkmode_dpll_abe			= 0x4a0051e0,
803 	.cm_idlest_dpll_abe			= 0x4a0051e4,
804 	.cm_autoidle_dpll_abe			= 0x4a0051e8,
805 	.cm_clksel_dpll_abe			= 0x4a0051ec,
806 	.cm_div_m2_dpll_abe			= 0x4a0051f0,
807 	.cm_div_m3_dpll_abe			= 0x4a0051f4,
808 	.cm_ssc_deltamstep_dpll_abe		= 0x4a005208,
809 	.cm_ssc_modfreqdiv_dpll_abe		= 0x4a00520c,
810 	.cm_clkmode_dpll_ddrphy			= 0x4a005210,
811 	.cm_idlest_dpll_ddrphy			= 0x4a005214,
812 	.cm_autoidle_dpll_ddrphy		= 0x4a005218,
813 	.cm_clksel_dpll_ddrphy			= 0x4a00521c,
814 	.cm_div_m2_dpll_ddrphy			= 0x4a005220,
815 	.cm_div_h11_dpll_ddrphy			= 0x4a005228,
816 	.cm_ssc_deltamstep_dpll_ddrphy		= 0x4a00522c,
817 	.cm_clkmode_dpll_dsp			= 0x4a005234,
818 	.cm_shadow_freq_config1			= 0x4a005260,
819 	.cm_clkmode_dpll_gmac			= 0x4a0052a8,
820 	.cm_coreaon_usb_phy1_core_clkctrl	= 0x4a008640,
821 	.cm_coreaon_usb_phy2_core_clkctrl	= 0x4a008688,
822 	.cm_coreaon_usb_phy3_core_clkctrl	= 0x4a008698,
823 	.cm_coreaon_l3init_60m_gfclk_clkctrl	= 0x4a0086c0,
824 
825 	/* cm1.mpu */
826 	.cm_mpu_mpu_clkctrl			= 0x4a005320,
827 
828 	/* cm1.dsp */
829 	.cm_dsp_clkstctrl			= 0x4a005400,
830 	.cm_dsp_dsp_clkctrl			= 0x4a005420,
831 
832 	/* cm IPU */
833 	.cm_ipu_clkstctrl			= 0x4a005540,
834 	.cm_ipu_i2c5_clkctrl			= 0x4a005578,
835 
836 	/* prm irqstatus regs */
837 	.prm_irqstatus_mpu			= 0x4ae06010,
838 	.prm_irqstatus_mpu_2			= 0x4ae06014,
839 
840 	/* cm2.ckgen */
841 	.cm_clksel_usb_60mhz			= 0x4a008104,
842 	.cm_clkmode_dpll_per			= 0x4a008140,
843 	.cm_idlest_dpll_per			= 0x4a008144,
844 	.cm_autoidle_dpll_per			= 0x4a008148,
845 	.cm_clksel_dpll_per			= 0x4a00814c,
846 	.cm_div_m2_dpll_per			= 0x4a008150,
847 	.cm_div_m3_dpll_per			= 0x4a008154,
848 	.cm_div_h11_dpll_per			= 0x4a008158,
849 	.cm_div_h12_dpll_per			= 0x4a00815c,
850 	.cm_div_h13_dpll_per			= 0x4a008160,
851 	.cm_div_h14_dpll_per			= 0x4a008164,
852 	.cm_ssc_deltamstep_dpll_per		= 0x4a008168,
853 	.cm_ssc_modfreqdiv_dpll_per		= 0x4a00816c,
854 	.cm_clkmode_dpll_usb			= 0x4a008180,
855 	.cm_idlest_dpll_usb			= 0x4a008184,
856 	.cm_autoidle_dpll_usb			= 0x4a008188,
857 	.cm_clksel_dpll_usb			= 0x4a00818c,
858 	.cm_div_m2_dpll_usb			= 0x4a008190,
859 	.cm_ssc_deltamstep_dpll_usb		= 0x4a0081a8,
860 	.cm_ssc_modfreqdiv_dpll_usb		= 0x4a0081ac,
861 	.cm_clkdcoldo_dpll_usb			= 0x4a0081b4,
862 	.cm_clkmode_dpll_pcie_ref		= 0x4a008200,
863 	.cm_clkmode_apll_pcie			= 0x4a00821c,
864 	.cm_idlest_apll_pcie			= 0x4a008220,
865 	.cm_div_m2_apll_pcie			= 0x4a008224,
866 	.cm_clkvcoldo_apll_pcie			= 0x4a008228,
867 
868 	/* cm2.core */
869 	.cm_l3_1_clkstctrl			= 0x4a008700,
870 	.cm_l3_1_dynamicdep			= 0x4a008708,
871 	.cm_l3_1_l3_1_clkctrl			= 0x4a008720,
872 	.cm_l3_gpmc_clkctrl			= 0x4a008728,
873 	.cm_mpu_m3_clkstctrl			= 0x4a008900,
874 	.cm_mpu_m3_staticdep			= 0x4a008904,
875 	.cm_mpu_m3_dynamicdep			= 0x4a008908,
876 	.cm_mpu_m3_mpu_m3_clkctrl		= 0x4a008920,
877 	.cm_sdma_clkstctrl			= 0x4a008a00,
878 	.cm_sdma_staticdep			= 0x4a008a04,
879 	.cm_sdma_dynamicdep			= 0x4a008a08,
880 	.cm_sdma_sdma_clkctrl			= 0x4a008a20,
881 	.cm_memif_clkstctrl			= 0x4a008b00,
882 	.cm_memif_dmm_clkctrl			= 0x4a008b20,
883 	.cm_memif_emif_fw_clkctrl		= 0x4a008b28,
884 	.cm_memif_emif_1_clkctrl		= 0x4a008b30,
885 	.cm_memif_emif_2_clkctrl		= 0x4a008b38,
886 	.cm_memif_dll_clkctrl			= 0x4a008b40,
887 	.cm_l4cfg_clkstctrl			= 0x4a008d00,
888 	.cm_l4cfg_dynamicdep			= 0x4a008d08,
889 	.cm_l4cfg_l4_cfg_clkctrl		= 0x4a008d20,
890 	.cm_l4cfg_hw_sem_clkctrl		= 0x4a008d28,
891 	.cm_l4cfg_mailbox_clkctrl		= 0x4a008d30,
892 	.cm_l4cfg_sar_rom_clkctrl		= 0x4a008d38,
893 	.cm_l3instr_clkstctrl			= 0x4a008e00,
894 	.cm_l3instr_l3_3_clkctrl		= 0x4a008e20,
895 	.cm_l3instr_l3_instr_clkctrl		= 0x4a008e28,
896 	.cm_l3instr_intrconn_wp1_clkctrl	= 0x4a008e40,
897 
898 	/* cm2.ivahd */
899 	.cm_ivahd_clkstctrl			= 0x4a008f00,
900 	.cm_ivahd_ivahd_clkctrl			= 0x4a008f20,
901 	.cm_ivahd_sl2_clkctrl			= 0x4a008f28,
902 
903 	/* cm2.cam */
904 	.cm_cam_clkstctrl			= 0x4a009000,
905 	.cm_cam_vip1_clkctrl			= 0x4a009020,
906 	.cm_cam_vip2_clkctrl			= 0x4a009028,
907 	.cm_cam_vip3_clkctrl			= 0x4a009030,
908 	.cm_cam_lvdsrx_clkctrl			= 0x4a009038,
909 	.cm_cam_csi1_clkctrl			= 0x4a009040,
910 	.cm_cam_csi2_clkctrl			= 0x4a009048,
911 
912 	/* cm2.dss */
913 	.cm_dss_clkstctrl			= 0x4a009100,
914 	.cm_dss_dss_clkctrl			= 0x4a009120,
915 
916 	/* cm2.sgx */
917 	.cm_sgx_clkstctrl			= 0x4a009200,
918 	.cm_sgx_sgx_clkctrl			= 0x4a009220,
919 
920 	/* cm2.l3init */
921 	.cm_l3init_clkstctrl			= 0x4a009300,
922 
923 	/* cm2.l3init */
924 	.cm_l3init_hsmmc1_clkctrl		= 0x4a009328,
925 	.cm_l3init_hsmmc2_clkctrl		= 0x4a009330,
926 	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
927 	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
928 	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
929 	.cm_l3init_sata_clkctrl			= 0x4a009388,
930 	.cm_gmac_clkstctrl			= 0x4a0093c0,
931 	.cm_gmac_gmac_clkctrl			= 0x4a0093d0,
932 	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
933 	.cm_l3init_ocp2scp3_clkctrl		= 0x4a0093e8,
934 	.cm_l3init_usb_otg_ss1_clkctrl		= 0x4a0093f0,
935 	.cm_l3init_usb_otg_ss2_clkctrl		= 0x4a009340,
936 
937 	/* cm2.l4per */
938 	.cm_l4per_clkstctrl			= 0x4a009700,
939 	.cm_l4per_dynamicdep			= 0x4a009708,
940 	.cm_l4per_gptimer10_clkctrl		= 0x4a009728,
941 	.cm_l4per_gptimer11_clkctrl		= 0x4a009730,
942 	.cm_l4per_gptimer2_clkctrl		= 0x4a009738,
943 	.cm_l4per_gptimer3_clkctrl		= 0x4a009740,
944 	.cm_l4per_gptimer4_clkctrl		= 0x4a009748,
945 	.cm_l4per_gptimer9_clkctrl		= 0x4a009750,
946 	.cm_l4per_elm_clkctrl			= 0x4a009758,
947 	.cm_l4per_gpio2_clkctrl			= 0x4a009760,
948 	.cm_l4per_gpio3_clkctrl			= 0x4a009768,
949 	.cm_l4per_gpio4_clkctrl			= 0x4a009770,
950 	.cm_l4per_gpio5_clkctrl			= 0x4a009778,
951 	.cm_l4per_gpio6_clkctrl			= 0x4a009780,
952 	.cm_l4per_hdq1w_clkctrl			= 0x4a009788,
953 	.cm_l4per_i2c1_clkctrl			= 0x4a0097a0,
954 	.cm_l4per_i2c2_clkctrl			= 0x4a0097a8,
955 	.cm_l4per_i2c3_clkctrl			= 0x4a0097b0,
956 	.cm_l4per_i2c4_clkctrl			= 0x4a0097b8,
957 	.cm_l4per_l4per_clkctrl			= 0x4a0097c0,
958 	.cm_l4per_mcspi1_clkctrl		= 0x4a0097f0,
959 	.cm_l4per_mcspi2_clkctrl		= 0x4a0097f8,
960 	.cm_l4per_mcspi3_clkctrl		= 0x4a009800,
961 	.cm_l4per_mcspi4_clkctrl		= 0x4a009808,
962 	.cm_l4per_gpio7_clkctrl			= 0x4a009810,
963 	.cm_l4per_gpio8_clkctrl			= 0x4a009818,
964 	.cm_l4per_mmcsd3_clkctrl		= 0x4a009820,
965 	.cm_l4per_mmcsd4_clkctrl		= 0x4a009828,
966 	.cm_l4per_qspi_clkctrl			= 0x4a009838,
967 	.cm_l4per_uart1_clkctrl			= 0x4a009840,
968 	.cm_l4per_uart2_clkctrl			= 0x4a009848,
969 	.cm_l4per_uart3_clkctrl			= 0x4a009850,
970 	.cm_l4per_uart4_clkctrl			= 0x4a009858,
971 	.cm_l4per_uart5_clkctrl			= 0x4a009870,
972 	.cm_l4sec_clkstctrl			= 0x4a009880,
973 	.cm_l4sec_staticdep			= 0x4a009884,
974 	.cm_l4sec_dynamicdep			= 0x4a009888,
975 	.cm_l4sec_aes1_clkctrl			= 0x4a0098a0,
976 	.cm_l4sec_aes2_clkctrl			= 0x4a0098a8,
977 	.cm_l4sec_des3des_clkctrl		= 0x4a0098b0,
978 	.cm_l4sec_rng_clkctrl			= 0x4a0098c0,
979 	.cm_l4sec_sha2md51_clkctrl		= 0x4a0098c8,
980 	.cm_l4sec_cryptodma_clkctrl		= 0x4a0098d8,
981 
982 	/* l4 wkup regs */
983 	.cm_abe_pll_ref_clksel			= 0x4ae0610c,
984 	.cm_sys_clksel				= 0x4ae06110,
985 	.cm_abe_pll_sys_clksel			= 0x4ae06118,
986 	.cm_wkup_clkstctrl			= 0x4ae07800,
987 	.cm_wkup_l4wkup_clkctrl			= 0x4ae07820,
988 	.cm_wkup_wdtimer1_clkctrl		= 0x4ae07828,
989 	.cm_wkup_wdtimer2_clkctrl		= 0x4ae07830,
990 	.cm_wkup_gpio1_clkctrl			= 0x4ae07838,
991 	.cm_wkup_gptimer1_clkctrl		= 0x4ae07840,
992 	.cm_wkup_gptimer12_clkctrl		= 0x4ae07848,
993 	.cm_wkup_sarram_clkctrl			= 0x4ae07860,
994 	.cm_wkup_keyboard_clkctrl		= 0x4ae07878,
995 	.cm_wkupaon_scrm_clkctrl		= 0x4ae07890,
996 	.prm_rstctrl				= 0x4ae07d00,
997 	.prm_rstst				= 0x4ae07d04,
998 	.prm_rsttime				= 0x4ae07d08,
999 	.prm_io_pmctrl				= 0x4ae07d20,
1000 	.prm_vc_val_bypass			= 0x4ae07da0,
1001 	.prm_vc_cfg_i2c_mode			= 0x4ae07db4,
1002 	.prm_vc_cfg_i2c_clk			= 0x4ae07db8,
1003 
1004 	.prm_abbldo_mpu_setup			= 0x4AE07DDC,
1005 	.prm_abbldo_mpu_ctrl			= 0x4AE07DE0,
1006 	.prm_abbldo_iva_setup			= 0x4AE07E34,
1007 	.prm_abbldo_iva_ctrl			= 0x4AE07E24,
1008 	.prm_abbldo_eve_setup			= 0x4AE07E30,
1009 	.prm_abbldo_eve_ctrl			= 0x4AE07E20,
1010 	.prm_abbldo_gpu_setup			= 0x4AE07DE4,
1011 	.prm_abbldo_gpu_ctrl			= 0x4AE07DE8,
1012 
1013 	/*l3main1 edma*/
1014 	.cm_l3main1_tptc1_clkctrl               = 0x4a008778,
1015 	.cm_l3main1_tptc2_clkctrl               = 0x4a008780,
1016 };
1017 
1018 void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
1019 {
1020 	u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 :
1021 		(*ctrl)->ctrl_core_sma_sw_0;
1022 	clrsetbits_le32(reg, clear_bits, set_bits);
1023 }
1024