1 /* 2 * 3 * Functions for omap5 based boards. 4 * 5 * (C) Copyright 2011 6 * Texas Instruments, <www.ti.com> 7 * 8 * Author : 9 * Aneesh V <aneesh@ti.com> 10 * Steve Sakoman <steve@sakoman.com> 11 * Sricharan <r.sricharan@ti.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0+ 14 */ 15 #include <common.h> 16 #include <palmas.h> 17 #include <asm/armv7.h> 18 #include <asm/arch/cpu.h> 19 #include <asm/arch/sys_proto.h> 20 #include <asm/arch/clock.h> 21 #include <linux/sizes.h> 22 #include <asm/utils.h> 23 #include <asm/arch/gpio.h> 24 #include <asm/emif.h> 25 #include <asm/omap_common.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; 30 31 #ifndef CONFIG_DM_GPIO 32 static struct gpio_bank gpio_bank_54xx[8] = { 33 { (void *)OMAP54XX_GPIO1_BASE }, 34 { (void *)OMAP54XX_GPIO2_BASE }, 35 { (void *)OMAP54XX_GPIO3_BASE }, 36 { (void *)OMAP54XX_GPIO4_BASE }, 37 { (void *)OMAP54XX_GPIO5_BASE }, 38 { (void *)OMAP54XX_GPIO6_BASE }, 39 { (void *)OMAP54XX_GPIO7_BASE }, 40 { (void *)OMAP54XX_GPIO8_BASE }, 41 }; 42 43 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx; 44 #endif 45 46 void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size) 47 { 48 int i; 49 struct pad_conf_entry *pad = (struct pad_conf_entry *)array; 50 51 for (i = 0; i < size; i++, pad++) 52 writel(pad->val, base + pad->offset); 53 } 54 55 #ifdef CONFIG_SPL_BUILD 56 /* LPDDR2 specific IO settings */ 57 static void io_settings_lpddr2(void) 58 { 59 const struct ctrl_ioregs *ioregs; 60 61 get_ioregs(&ioregs); 62 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); 63 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); 64 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); 65 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); 66 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); 67 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); 68 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); 69 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); 70 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); 71 } 72 73 /* DDR3 specific IO settings */ 74 static void io_settings_ddr3(void) 75 { 76 u32 io_settings = 0; 77 const struct ctrl_ioregs *ioregs; 78 79 get_ioregs(&ioregs); 80 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0); 81 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0); 82 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1); 83 84 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0); 85 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0); 86 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1); 87 88 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0); 89 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1); 90 91 if (!is_dra7xx()) { 92 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2); 93 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1); 94 } 95 96 /* omap5432 does not use lpddr2 */ 97 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0); 98 99 writel(ioregs->ctrl_emif_sdram_config_ext, 100 (*ctrl)->control_emif1_sdram_config_ext); 101 if (!is_dra72x()) 102 writel(ioregs->ctrl_emif_sdram_config_ext, 103 (*ctrl)->control_emif2_sdram_config_ext); 104 105 if (is_omap54xx()) { 106 /* Disable DLL select */ 107 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) 108 & 0xFFEFFFFF); 109 writel(io_settings, 110 (*ctrl)->control_port_emif1_sdram_config); 111 112 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) 113 & 0xFFEFFFFF); 114 writel(io_settings, 115 (*ctrl)->control_port_emif2_sdram_config); 116 } else { 117 writel(ioregs->ctrl_ddr_ctrl_ext_0, 118 (*ctrl)->control_ddr_control_ext_0); 119 } 120 } 121 122 /* 123 * Some tuning of IOs for optimal power and performance 124 */ 125 void do_io_settings(void) 126 { 127 u32 io_settings = 0, mask = 0; 128 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; 129 130 /* Impedance settings EMMC, C2C 1,2, hsi2 */ 131 mask = (ds_mask << 2) | (ds_mask << 8) | 132 (ds_mask << 16) | (ds_mask << 18); 133 io_settings = readl((*ctrl)->control_smart1io_padconf_0) & 134 (~mask); 135 io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) | 136 (ds_45_ohm << 18) | (ds_60_ohm << 2); 137 writel(io_settings, (*ctrl)->control_smart1io_padconf_0); 138 139 /* Impedance settings Mcspi2 */ 140 mask = (ds_mask << 30); 141 io_settings = readl((*ctrl)->control_smart1io_padconf_1) & 142 (~mask); 143 io_settings |= (ds_60_ohm << 30); 144 writel(io_settings, (*ctrl)->control_smart1io_padconf_1); 145 146 /* Impedance settings C2C 3,4 */ 147 mask = (ds_mask << 14) | (ds_mask << 16); 148 io_settings = readl((*ctrl)->control_smart1io_padconf_2) & 149 (~mask); 150 io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16); 151 writel(io_settings, (*ctrl)->control_smart1io_padconf_2); 152 153 /* Slew rate settings EMMC, C2C 1,2 */ 154 mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18); 155 io_settings = readl((*ctrl)->control_smart2io_padconf_0) & 156 (~mask); 157 io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18); 158 writel(io_settings, (*ctrl)->control_smart2io_padconf_0); 159 160 /* Slew rate settings hsi2, Mcspi2 */ 161 mask = (sc_mask << 24) | (sc_mask << 28); 162 io_settings = readl((*ctrl)->control_smart2io_padconf_1) & 163 (~mask); 164 io_settings |= (sc_fast << 28) | (sc_fast << 24); 165 writel(io_settings, (*ctrl)->control_smart2io_padconf_1); 166 167 /* Slew rate settings C2C 3,4 */ 168 mask = (sc_mask << 16) | (sc_mask << 18); 169 io_settings = readl((*ctrl)->control_smart2io_padconf_2) & 170 (~mask); 171 io_settings |= (sc_na << 16) | (sc_na << 18); 172 writel(io_settings, (*ctrl)->control_smart2io_padconf_2); 173 174 /* impedance and slew rate settings for usb */ 175 mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) | 176 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14); 177 io_settings = readl((*ctrl)->control_smart3io_padconf_1) & 178 (~mask); 179 io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) | 180 (ds_60_ohm << 23) | (sc_fast << 20) | 181 (sc_fast << 17) | (sc_fast << 14); 182 writel(io_settings, (*ctrl)->control_smart3io_padconf_1); 183 184 if (emif_sdram_type(emif->emif_sdram_config) == EMIF_SDRAM_TYPE_LPDDR2) 185 io_settings_lpddr2(); 186 else 187 io_settings_ddr3(); 188 } 189 190 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { 191 {0x45, 0x1}, /* 12 MHz */ 192 {-1, -1}, /* 13 MHz */ 193 {0x63, 0x2}, /* 16.8 MHz */ 194 {0x57, 0x2}, /* 19.2 MHz */ 195 {0x20, 0x1}, /* 26 MHz */ 196 {-1, -1}, /* 27 MHz */ 197 {0x41, 0x3} /* 38.4 MHz */ 198 }; 199 200 void srcomp_enable(void) 201 { 202 u32 srcomp_value, mul_factor, div_factor, clk_val, i; 203 u32 sysclk_ind = get_sys_clk_index(); 204 u32 omap_rev = omap_revision(); 205 206 if (!is_omap54xx()) 207 return; 208 209 mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; 210 div_factor = srcomp_parameters[sysclk_ind].divide_factor; 211 212 for (i = 0; i < 4; i++) { 213 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); 214 srcomp_value &= 215 ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); 216 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | 217 (div_factor << DIVIDE_FACTOR_XS_SHIFT); 218 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); 219 } 220 221 if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { 222 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); 223 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; 224 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); 225 226 for (i = 0; i < 4; i++) { 227 srcomp_value = 228 readl((*ctrl)->control_srcomp_north_side + i*4); 229 srcomp_value &= ~PWRDWN_XS_MASK; 230 writel(srcomp_value, 231 (*ctrl)->control_srcomp_north_side + i*4); 232 233 while (((readl((*ctrl)->control_srcomp_north_side + i*4) 234 & SRCODE_READ_XS_MASK) >> 235 SRCODE_READ_XS_SHIFT) == 0) 236 ; 237 238 srcomp_value = 239 readl((*ctrl)->control_srcomp_north_side + i*4); 240 srcomp_value &= ~OVERRIDE_XS_MASK; 241 writel(srcomp_value, 242 (*ctrl)->control_srcomp_north_side + i*4); 243 } 244 } else { 245 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); 246 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | 247 DIVIDE_FACTOR_XS_MASK); 248 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | 249 (div_factor << DIVIDE_FACTOR_XS_SHIFT); 250 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); 251 252 for (i = 0; i < 4; i++) { 253 srcomp_value = 254 readl((*ctrl)->control_srcomp_north_side + i*4); 255 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; 256 writel(srcomp_value, 257 (*ctrl)->control_srcomp_north_side + i*4); 258 259 srcomp_value = 260 readl((*ctrl)->control_srcomp_north_side + i*4); 261 srcomp_value &= ~OVERRIDE_XS_MASK; 262 writel(srcomp_value, 263 (*ctrl)->control_srcomp_north_side + i*4); 264 } 265 266 srcomp_value = 267 readl((*ctrl)->control_srcomp_east_side_wkup); 268 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; 269 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); 270 271 srcomp_value = 272 readl((*ctrl)->control_srcomp_east_side_wkup); 273 srcomp_value &= ~OVERRIDE_XS_MASK; 274 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); 275 276 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); 277 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; 278 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); 279 280 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); 281 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; 282 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); 283 284 for (i = 0; i < 4; i++) { 285 while (((readl((*ctrl)->control_srcomp_north_side + i*4) 286 & SRCODE_READ_XS_MASK) >> 287 SRCODE_READ_XS_SHIFT) == 0) 288 ; 289 290 srcomp_value = 291 readl((*ctrl)->control_srcomp_north_side + i*4); 292 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; 293 writel(srcomp_value, 294 (*ctrl)->control_srcomp_north_side + i*4); 295 } 296 297 while (((readl((*ctrl)->control_srcomp_east_side_wkup) & 298 SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) 299 ; 300 301 srcomp_value = 302 readl((*ctrl)->control_srcomp_east_side_wkup); 303 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; 304 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); 305 } 306 } 307 #endif 308 309 void config_data_eye_leveling_samples(u32 emif_base) 310 { 311 const struct ctrl_ioregs *ioregs; 312 313 get_ioregs(&ioregs); 314 315 /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ 316 if (emif_base == EMIF1_BASE) 317 writel(ioregs->ctrl_emif_sdram_config_ext_final, 318 (*ctrl)->control_emif1_sdram_config_ext); 319 else if (emif_base == EMIF2_BASE) 320 writel(ioregs->ctrl_emif_sdram_config_ext_final, 321 (*ctrl)->control_emif2_sdram_config_ext); 322 } 323 324 void init_cpu_configuration(void) 325 { 326 u32 l2actlr; 327 328 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r"(l2actlr)); 329 /* 330 * L2ACTLR: Ensure to enable the following: 331 * 3: Disable clean/evict push to external 332 * 4: Disable WriteUnique and WriteLineUnique transactions from master 333 * 8: Disable DVM/CMO message broadcast 334 */ 335 l2actlr |= 0x118; 336 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2actlr); 337 } 338 339 void init_omap_revision(void) 340 { 341 /* 342 * For some of the ES2/ES1 boards ID_CODE is not reliable: 343 * Also, ES1 and ES2 have different ARM revisions 344 * So use ARM revision for identification 345 */ 346 unsigned int rev = cortex_rev(); 347 348 switch (readl(CONTROL_ID_CODE)) { 349 case OMAP5430_CONTROL_ID_CODE_ES1_0: 350 *omap_si_rev = OMAP5430_ES1_0; 351 if (rev == MIDR_CORTEX_A15_R2P2) 352 *omap_si_rev = OMAP5430_ES2_0; 353 break; 354 case OMAP5432_CONTROL_ID_CODE_ES1_0: 355 *omap_si_rev = OMAP5432_ES1_0; 356 if (rev == MIDR_CORTEX_A15_R2P2) 357 *omap_si_rev = OMAP5432_ES2_0; 358 break; 359 case OMAP5430_CONTROL_ID_CODE_ES2_0: 360 *omap_si_rev = OMAP5430_ES2_0; 361 break; 362 case OMAP5432_CONTROL_ID_CODE_ES2_0: 363 *omap_si_rev = OMAP5432_ES2_0; 364 break; 365 case DRA752_CONTROL_ID_CODE_ES1_0: 366 *omap_si_rev = DRA752_ES1_0; 367 break; 368 case DRA752_CONTROL_ID_CODE_ES1_1: 369 *omap_si_rev = DRA752_ES1_1; 370 break; 371 case DRA752_CONTROL_ID_CODE_ES2_0: 372 *omap_si_rev = DRA752_ES2_0; 373 break; 374 case DRA722_CONTROL_ID_CODE_ES1_0: 375 *omap_si_rev = DRA722_ES1_0; 376 break; 377 case DRA722_CONTROL_ID_CODE_ES2_0: 378 *omap_si_rev = DRA722_ES2_0; 379 break; 380 default: 381 *omap_si_rev = OMAP5430_SILICON_ID_INVALID; 382 } 383 init_cpu_configuration(); 384 } 385 386 void omap_die_id(unsigned int *die_id) 387 { 388 die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); 389 die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); 390 die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); 391 die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); 392 } 393 394 void reset_cpu(ulong ignored) 395 { 396 u32 omap_rev = omap_revision(); 397 398 /* 399 * WARM reset is not functional in case of OMAP5430 ES1.0 soc. 400 * So use cold reset in case instead. 401 */ 402 if (omap_rev == OMAP5430_ES1_0) 403 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl); 404 else 405 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl); 406 } 407 408 u32 warm_reset(void) 409 { 410 return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK; 411 } 412 413 void setup_warmreset_time(void) 414 { 415 u32 rst_time, rst_val; 416 417 /* 418 * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff. 419 * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles 420 * into microsec and passing the value. 421 */ 422 rst_time = usec_to_32k(CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC) 423 << RSTTIME1_SHIFT; 424 425 if (rst_time > RSTTIME1_MASK) 426 rst_time = RSTTIME1_MASK; 427 428 rst_val = readl((*prcm)->prm_rsttime) & ~RSTTIME1_MASK; 429 rst_val |= rst_time; 430 writel(rst_val, (*prcm)->prm_rsttime); 431 } 432 433 void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr, 434 u32 cpu_rev_comb, u32 cpu_variant, 435 u32 cpu_rev) 436 { 437 omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl); 438 } 439 440 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb, 441 u32 cpu_variant, u32 cpu_rev) 442 { 443 444 #ifdef CONFIG_ARM_ERRATA_801819 445 /* 446 * DRA72x processors are uniprocessors and DONOT have 447 * ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency 448 * Extensions) Hence the erratum workaround is not applicable for 449 * DRA72x processors. 450 */ 451 if (is_dra72x()) 452 acr &= ~((0x3 << 23) | (0x3 << 25)); 453 #endif 454 omap_smc1(OMAP5_SERVICE_ACR_SET, acr); 455 } 456 457 #if defined(CONFIG_PALMAS_POWER) 458 void vmmc_pbias_config(uint voltage) 459 { 460 u32 value = 0; 461 struct vcores_data const *vcores = *omap_vcores; 462 463 value = readl((*ctrl)->control_pbias); 464 value &= ~SDCARD_PWRDNZ; 465 writel(value, (*ctrl)->control_pbias); 466 udelay(10); /* wait 10 us */ 467 value &= ~SDCARD_BIAS_PWRDNZ; 468 writel(value, (*ctrl)->control_pbias); 469 470 if (vcores->core.pmic->i2c_slave_addr == 0x60) { 471 if (voltage == LDO_VOLT_3V0) 472 voltage = 0x19; 473 else if (voltage == LDO_VOLT_1V8) 474 voltage = 0xa; 475 lp873x_mmc1_poweron_ldo(voltage); 476 } else { 477 palmas_mmc1_poweron_ldo(voltage); 478 } 479 480 value = readl((*ctrl)->control_pbias); 481 value |= SDCARD_BIAS_PWRDNZ; 482 writel(value, (*ctrl)->control_pbias); 483 udelay(150); /* wait 150 us */ 484 value |= SDCARD_PWRDNZ; 485 writel(value, (*ctrl)->control_pbias); 486 udelay(150); /* wait 150 us */ 487 } 488 #endif 489