1 /* 2 * 3 * HW data initialization for OMAP5 4 * 5 * (C) Copyright 2013 6 * Texas Instruments, <www.ti.com> 7 * 8 * Sricharan R <r.sricharan@ti.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #include <common.h> 13 #include <palmas.h> 14 #include <asm/arch/omap.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/omap_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/omap_gpio.h> 19 #include <asm/io.h> 20 #include <asm/emif.h> 21 22 struct prcm_regs const **prcm = 23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; 24 struct dplls const **dplls_data = 25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; 26 struct vcores_data const **omap_vcores = 27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; 28 struct omap_sys_ctrl_regs const **ctrl = 29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; 30 31 /* OPP NOM FREQUENCY for ES1.0 */ 32 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { 33 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 35 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 36 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 37 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 39 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 40 }; 41 42 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ 43 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { 44 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 45 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 46 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 47 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 48 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 50 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 51 }; 52 53 static const struct dpll_params 54 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { 55 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ 56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 57 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ 58 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ 59 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ 60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 61 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ 62 }; 63 64 static const struct dpll_params 65 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { 66 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ 67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 68 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ 69 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ 70 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ 71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 72 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ 73 }; 74 75 static const struct dpll_params 76 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { 77 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ 78 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ 79 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ 80 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ 81 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ 82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 83 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ 84 }; 85 86 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { 87 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 88 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 89 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 90 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 91 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 92 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 93 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 94 }; 95 96 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { 97 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 98 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 99 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 100 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 101 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 102 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 103 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 104 }; 105 106 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { 107 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ 108 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ 109 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 110 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 111 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ 112 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 113 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 114 }; 115 116 static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = { 117 {32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 12 MHz */ 118 {96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 20 MHz */ 119 {160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 120 {20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 121 {192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 26 MHz */ 122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 123 {10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 124 }; 125 126 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { 127 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 128 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 129 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 130 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 131 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 132 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 133 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 134 }; 135 136 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { 137 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 138 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 139 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 140 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 141 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 142 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 143 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 144 }; 145 146 /* ABE M & N values with sys_clk as source */ 147 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 148 static const struct dpll_params 149 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { 150 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 151 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 152 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 153 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 154 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 155 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 156 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 157 }; 158 #endif 159 160 /* ABE M & N values with 32K clock as source */ 161 #ifndef CONFIG_SYS_OMAP_ABE_SYSCK 162 static const struct dpll_params abe_dpll_params_32k_196608khz = { 163 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 164 }; 165 #endif 166 167 /* ABE M & N values with sysclk2(22.5792 MHz) as input */ 168 static const struct dpll_params 169 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { 170 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 171 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 172 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 174 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 175 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 176 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 177 }; 178 179 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { 180 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 181 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 182 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 183 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 184 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 185 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 186 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 187 }; 188 189 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { 190 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 191 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 192 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 193 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 194 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 196 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 197 }; 198 199 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { 200 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 201 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 202 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 203 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 204 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 205 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 206 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 207 }; 208 209 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { 210 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ 211 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ 212 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 213 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 214 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ 215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 216 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 217 }; 218 219 struct dplls omap5_dplls_es1 = { 220 .mpu = mpu_dpll_params_800mhz, 221 .core = core_dpll_params_2128mhz_ddr532, 222 .per = per_dpll_params_768mhz, 223 .iva = iva_dpll_params_2330mhz, 224 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 225 .abe = abe_dpll_params_sysclk_196608khz, 226 #else 227 .abe = &abe_dpll_params_32k_196608khz, 228 #endif 229 .usb = usb_dpll_params_1920mhz, 230 .ddr = NULL 231 }; 232 233 struct dplls omap5_dplls_es2 = { 234 .mpu = mpu_dpll_params_1ghz, 235 .core = core_dpll_params_2128mhz_ddr532_es2, 236 .per = per_dpll_params_768mhz_es2, 237 .iva = iva_dpll_params_2330mhz, 238 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 239 .abe = abe_dpll_params_sysclk_196608khz, 240 #else 241 .abe = &abe_dpll_params_32k_196608khz, 242 #endif 243 .usb = usb_dpll_params_1920mhz, 244 .ddr = NULL 245 }; 246 247 struct dplls dra76x_dplls = { 248 .mpu = mpu_dpll_params_1ghz, 249 .core = core_dpll_params_2128mhz_dra7xx, 250 .per = per_dpll_params_768mhz_dra76x, 251 .abe = abe_dpll_params_sysclk2_361267khz, 252 .iva = iva_dpll_params_2330mhz_dra7xx, 253 .usb = usb_dpll_params_1920mhz, 254 .ddr = ddr_dpll_params_2664mhz, 255 .gmac = gmac_dpll_params_2000mhz, 256 }; 257 258 struct dplls dra7xx_dplls = { 259 .mpu = mpu_dpll_params_1ghz, 260 .core = core_dpll_params_2128mhz_dra7xx, 261 .per = per_dpll_params_768mhz_dra7xx, 262 .abe = abe_dpll_params_sysclk2_361267khz, 263 .iva = iva_dpll_params_2330mhz_dra7xx, 264 .usb = usb_dpll_params_1920mhz, 265 .ddr = ddr_dpll_params_2128mhz, 266 .gmac = gmac_dpll_params_2000mhz, 267 }; 268 269 struct dplls dra72x_dplls = { 270 .mpu = mpu_dpll_params_1ghz, 271 .core = core_dpll_params_2128mhz_dra7xx, 272 .per = per_dpll_params_768mhz_dra7xx, 273 .abe = abe_dpll_params_sysclk2_361267khz, 274 .iva = iva_dpll_params_2330mhz_dra7xx, 275 .usb = usb_dpll_params_1920mhz, 276 .ddr = ddr_dpll_params_2664mhz, 277 .gmac = gmac_dpll_params_2000mhz, 278 }; 279 280 struct pmic_data palmas = { 281 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 282 .step = 10000, /* 10 mV represented in uV */ 283 /* 284 * Offset codes 1-6 all give the base voltage in Palmas 285 * Offset code 0 switches OFF the SMPS 286 */ 287 .start_code = 6, 288 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, 289 .pmic_bus_init = sri2c_init, 290 .pmic_write = omap_vc_bypass_send_value, 291 .gpio_en = 0, 292 }; 293 294 /* The TPS659038 and TPS65917 are software-compatible, use common struct */ 295 struct pmic_data tps659038 = { 296 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 297 .step = 10000, /* 10 mV represented in uV */ 298 /* 299 * Offset codes 1-6 all give the base voltage in Palmas 300 * Offset code 0 switches OFF the SMPS 301 */ 302 .start_code = 6, 303 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, 304 .pmic_bus_init = gpi2c_init, 305 .pmic_write = palmas_i2c_write_u8, 306 .gpio_en = 0, 307 }; 308 309 /* The LP87565*/ 310 struct pmic_data lp87565 = { 311 .base_offset = LP873X_BUCK_BASE_VOLT_UV, 312 .step = 5000, /* 5 mV represented in uV */ 313 /* 314 * Offset codes 0 - 0x13 Invalid. 315 * Offset codes 0x14 0x17 give 10mV steps 316 * Offset codes 0x17 through 0x9D give 5mV steps 317 * So let us start with our operating range from .73V 318 */ 319 .start_code = 0x17, 320 .i2c_slave_addr = 0x60, 321 .pmic_bus_init = gpi2c_init, 322 .pmic_write = palmas_i2c_write_u8, 323 }; 324 325 /* The LP8732 and LP8733 are software-compatible, use common struct */ 326 struct pmic_data lp8733 = { 327 .base_offset = LP873X_BUCK_BASE_VOLT_UV, 328 .step = 5000, /* 5 mV represented in uV */ 329 /* 330 * Offset codes 0 - 0x13 Invalid. 331 * Offset codes 0x14 0x17 give 10mV steps 332 * Offset codes 0x17 through 0x9D give 5mV steps 333 * So let us start with our operating range from .73V 334 */ 335 .start_code = 0x17, 336 .i2c_slave_addr = 0x60, 337 .pmic_bus_init = gpi2c_init, 338 .pmic_write = palmas_i2c_write_u8, 339 }; 340 341 struct vcores_data omap5430_volts = { 342 .mpu.value[OPP_NOM] = VDD_MPU, 343 .mpu.addr = SMPS_REG_ADDR_12_MPU, 344 .mpu.pmic = &palmas, 345 346 .core.value[OPP_NOM] = VDD_CORE, 347 .core.addr = SMPS_REG_ADDR_8_CORE, 348 .core.pmic = &palmas, 349 350 .mm.value[OPP_NOM] = VDD_MM, 351 .mm.addr = SMPS_REG_ADDR_45_IVA, 352 .mm.pmic = &palmas, 353 }; 354 355 struct vcores_data omap5430_volts_es2 = { 356 .mpu.value[OPP_NOM] = VDD_MPU_ES2, 357 .mpu.addr = SMPS_REG_ADDR_12_MPU, 358 .mpu.pmic = &palmas, 359 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 360 361 .core.value[OPP_NOM] = VDD_CORE_ES2, 362 .core.addr = SMPS_REG_ADDR_8_CORE, 363 .core.pmic = &palmas, 364 365 .mm.value[OPP_NOM] = VDD_MM_ES2, 366 .mm.addr = SMPS_REG_ADDR_45_IVA, 367 .mm.pmic = &palmas, 368 .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, 369 370 .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN, 371 .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, 372 373 .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN, 374 .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, 375 376 .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN, 377 .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, 378 }; 379 380 /* 381 * Enable essential clock domains, modules and 382 * do some additional special settings needed 383 */ 384 void enable_basic_clocks(void) 385 { 386 u32 const clk_domains_essential[] = { 387 (*prcm)->cm_l4per_clkstctrl, 388 (*prcm)->cm_l3init_clkstctrl, 389 (*prcm)->cm_memif_clkstctrl, 390 (*prcm)->cm_l4cfg_clkstctrl, 391 #ifdef CONFIG_DRIVER_TI_CPSW 392 (*prcm)->cm_gmac_clkstctrl, 393 #endif 394 0 395 }; 396 397 u32 const clk_modules_hw_auto_essential[] = { 398 (*prcm)->cm_l3_gpmc_clkctrl, 399 (*prcm)->cm_memif_emif_1_clkctrl, 400 (*prcm)->cm_memif_emif_2_clkctrl, 401 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, 402 (*prcm)->cm_wkup_gpio1_clkctrl, 403 (*prcm)->cm_l4per_gpio2_clkctrl, 404 (*prcm)->cm_l4per_gpio3_clkctrl, 405 (*prcm)->cm_l4per_gpio4_clkctrl, 406 (*prcm)->cm_l4per_gpio5_clkctrl, 407 (*prcm)->cm_l4per_gpio6_clkctrl, 408 (*prcm)->cm_l4per_gpio7_clkctrl, 409 (*prcm)->cm_l4per_gpio8_clkctrl, 410 #ifdef CONFIG_SCSI_AHCI_PLAT 411 (*prcm)->cm_l3init_ocp2scp3_clkctrl, 412 #endif 413 0 414 }; 415 416 u32 const clk_modules_explicit_en_essential[] = { 417 (*prcm)->cm_wkup_gptimer1_clkctrl, 418 (*prcm)->cm_l3init_hsmmc1_clkctrl, 419 (*prcm)->cm_l3init_hsmmc2_clkctrl, 420 (*prcm)->cm_l4per_gptimer2_clkctrl, 421 (*prcm)->cm_wkup_wdtimer2_clkctrl, 422 (*prcm)->cm_l4per_uart3_clkctrl, 423 (*prcm)->cm_l4per_i2c1_clkctrl, 424 #ifdef CONFIG_DRIVER_TI_CPSW 425 (*prcm)->cm_gmac_gmac_clkctrl, 426 #endif 427 428 #ifdef CONFIG_TI_QSPI 429 (*prcm)->cm_l4per_qspi_clkctrl, 430 #endif 431 #ifdef CONFIG_SCSI_AHCI_PLAT 432 (*prcm)->cm_l3init_sata_clkctrl, 433 #endif 434 0 435 }; 436 437 /* Enable optional additional functional clock for GPIO4 */ 438 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, 439 GPIO4_CLKCTRL_OPTFCLKEN_MASK); 440 441 /* Enable 192 MHz clock for MMC1 & MMC2 */ 442 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 443 HSMMC_CLKCTRL_CLKSEL_MASK); 444 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 445 HSMMC_CLKCTRL_CLKSEL_MASK); 446 447 /* Set the correct clock dividers for mmc */ 448 clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 449 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 450 clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 451 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 452 453 /* Select 32KHz clock as the source of GPTIMER1 */ 454 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, 455 GPTIMER1_CLKCTRL_CLKSEL_MASK); 456 457 do_enable_clocks(clk_domains_essential, 458 clk_modules_hw_auto_essential, 459 clk_modules_explicit_en_essential, 460 1); 461 462 #ifdef CONFIG_TI_QSPI 463 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); 464 #endif 465 466 #ifdef CONFIG_SCSI_AHCI_PLAT 467 /* Enable optional functional clock for SATA */ 468 setbits_le32((*prcm)->cm_l3init_sata_clkctrl, 469 SATA_CLKCTRL_OPTFCLKEN_MASK); 470 #endif 471 472 /* Enable SCRM OPT clocks for PER and CORE dpll */ 473 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 474 OPTFCLKEN_SCRM_PER_MASK); 475 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 476 OPTFCLKEN_SCRM_CORE_MASK); 477 } 478 479 void enable_basic_uboot_clocks(void) 480 { 481 u32 const clk_domains_essential[] = { 482 #if defined(CONFIG_DRA7XX) 483 (*prcm)->cm_ipu_clkstctrl, 484 #endif 485 0 486 }; 487 488 u32 const clk_modules_hw_auto_essential[] = { 489 (*prcm)->cm_l3init_hsusbtll_clkctrl, 490 0 491 }; 492 493 u32 const clk_modules_explicit_en_essential[] = { 494 (*prcm)->cm_l4per_mcspi1_clkctrl, 495 (*prcm)->cm_l4per_i2c2_clkctrl, 496 (*prcm)->cm_l4per_i2c3_clkctrl, 497 (*prcm)->cm_l4per_i2c4_clkctrl, 498 #if defined(CONFIG_DRA7XX) 499 (*prcm)->cm_ipu_i2c5_clkctrl, 500 #else 501 (*prcm)->cm_l4per_i2c5_clkctrl, 502 #endif 503 (*prcm)->cm_l3init_hsusbhost_clkctrl, 504 (*prcm)->cm_l3init_fsusb_clkctrl, 505 0 506 }; 507 do_enable_clocks(clk_domains_essential, 508 clk_modules_hw_auto_essential, 509 clk_modules_explicit_en_essential, 510 1); 511 } 512 513 #ifdef CONFIG_TI_EDMA3 514 void enable_edma3_clocks(void) 515 { 516 u32 const clk_domains_edma3[] = { 517 0 518 }; 519 520 u32 const clk_modules_hw_auto_edma3[] = { 521 (*prcm)->cm_l3main1_tptc1_clkctrl, 522 (*prcm)->cm_l3main1_tptc2_clkctrl, 523 0 524 }; 525 526 u32 const clk_modules_explicit_en_edma3[] = { 527 0 528 }; 529 530 do_enable_clocks(clk_domains_edma3, 531 clk_modules_hw_auto_edma3, 532 clk_modules_explicit_en_edma3, 533 1); 534 } 535 536 void disable_edma3_clocks(void) 537 { 538 u32 const clk_domains_edma3[] = { 539 0 540 }; 541 542 u32 const clk_modules_disable_edma3[] = { 543 (*prcm)->cm_l3main1_tptc1_clkctrl, 544 (*prcm)->cm_l3main1_tptc2_clkctrl, 545 0 546 }; 547 548 do_disable_clocks(clk_domains_edma3, 549 clk_modules_disable_edma3, 550 1); 551 } 552 #endif 553 554 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 555 void enable_usb_clocks(int index) 556 { 557 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 558 559 if (index == 0) { 560 cm_l3init_usb_otg_ss_clkctrl = 561 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 562 /* Enable 960 MHz clock for dwc3 */ 563 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 564 OPTFCLKEN_REFCLK960M); 565 566 /* Enable 32 KHz clock for USB_PHY1 */ 567 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 568 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 569 570 /* Enable 32 KHz clock for USB_PHY3 */ 571 if (is_dra7xx()) 572 setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 573 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 574 } else if (index == 1) { 575 cm_l3init_usb_otg_ss_clkctrl = 576 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 577 /* Enable 960 MHz clock for dwc3 */ 578 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 579 OPTFCLKEN_REFCLK960M); 580 581 /* Enable 32 KHz clock for dwc3 */ 582 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 583 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 584 585 /* Enable 60 MHz clock for USB2PHY2 */ 586 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 587 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 588 } 589 590 u32 const clk_domains_usb[] = { 591 0 592 }; 593 594 u32 const clk_modules_hw_auto_usb[] = { 595 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 596 cm_l3init_usb_otg_ss_clkctrl, 597 0 598 }; 599 600 u32 const clk_modules_explicit_en_usb[] = { 601 0 602 }; 603 604 do_enable_clocks(clk_domains_usb, 605 clk_modules_hw_auto_usb, 606 clk_modules_explicit_en_usb, 607 1); 608 } 609 610 void disable_usb_clocks(int index) 611 { 612 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 613 614 if (index == 0) { 615 cm_l3init_usb_otg_ss_clkctrl = 616 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 617 /* Disable 960 MHz clock for dwc3 */ 618 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 619 OPTFCLKEN_REFCLK960M); 620 621 /* Disable 32 KHz clock for USB_PHY1 */ 622 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 623 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 624 625 /* Disable 32 KHz clock for USB_PHY3 */ 626 if (is_dra7xx()) 627 clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 628 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 629 } else if (index == 1) { 630 cm_l3init_usb_otg_ss_clkctrl = 631 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 632 /* Disable 960 MHz clock for dwc3 */ 633 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 634 OPTFCLKEN_REFCLK960M); 635 636 /* Disable 32 KHz clock for dwc3 */ 637 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 638 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 639 640 /* Disable 60 MHz clock for USB2PHY2 */ 641 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 642 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 643 } 644 645 u32 const clk_domains_usb[] = { 646 0 647 }; 648 649 u32 const clk_modules_disable[] = { 650 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 651 cm_l3init_usb_otg_ss_clkctrl, 652 0 653 }; 654 655 do_disable_clocks(clk_domains_usb, 656 clk_modules_disable, 657 1); 658 } 659 #endif 660 661 const struct ctrl_ioregs ioregs_omap5430 = { 662 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, 663 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, 664 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, 665 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, 666 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, 667 }; 668 669 const struct ctrl_ioregs ioregs_omap5432_es1 = { 670 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, 671 .ctrl_lpddr2ch = 0x0, 672 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, 673 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, 674 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, 675 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, 676 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 677 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 678 }; 679 680 const struct ctrl_ioregs ioregs_omap5432_es2 = { 681 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 682 .ctrl_lpddr2ch = 0x0, 683 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 684 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, 685 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, 686 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, 687 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 688 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 689 }; 690 691 const struct ctrl_ioregs ioregs_dra7xx_es1 = { 692 .ctrl_ddrch = 0x40404040, 693 .ctrl_lpddr2ch = 0x40404040, 694 .ctrl_ddr3ch = 0x80808080, 695 .ctrl_ddrio_0 = 0x00094A40, 696 .ctrl_ddrio_1 = 0x04A52000, 697 .ctrl_ddrio_2 = 0x84210000, 698 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 699 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 700 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 701 }; 702 703 const struct ctrl_ioregs ioregs_dra72x_es1 = { 704 .ctrl_ddrch = 0x40404040, 705 .ctrl_lpddr2ch = 0x40404040, 706 .ctrl_ddr3ch = 0x60606080, 707 .ctrl_ddrio_0 = 0x00094A40, 708 .ctrl_ddrio_1 = 0x04A52000, 709 .ctrl_ddrio_2 = 0x84210000, 710 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 711 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 712 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 713 }; 714 715 const struct ctrl_ioregs ioregs_dra72x_es2 = { 716 .ctrl_ddrch = 0x40404040, 717 .ctrl_lpddr2ch = 0x40404040, 718 .ctrl_ddr3ch = 0x60606060, 719 .ctrl_ddrio_0 = 0x00094A40, 720 .ctrl_ddrio_1 = 0x00000000, 721 .ctrl_ddrio_2 = 0x00000000, 722 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 723 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 724 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 725 }; 726 727 void __weak hw_data_init(void) 728 { 729 u32 omap_rev = omap_revision(); 730 731 switch (omap_rev) { 732 733 case OMAP5430_ES1_0: 734 case OMAP5432_ES1_0: 735 *prcm = &omap5_es1_prcm; 736 *dplls_data = &omap5_dplls_es1; 737 *omap_vcores = &omap5430_volts; 738 *ctrl = &omap5_ctrl; 739 break; 740 741 case OMAP5430_ES2_0: 742 case OMAP5432_ES2_0: 743 *prcm = &omap5_es2_prcm; 744 *dplls_data = &omap5_dplls_es2; 745 *omap_vcores = &omap5430_volts_es2; 746 *ctrl = &omap5_ctrl; 747 break; 748 749 case DRA762_ABZ_ES1_0: 750 case DRA762_ACD_ES1_0: 751 case DRA762_ES1_0: 752 *prcm = &dra7xx_prcm; 753 *dplls_data = &dra76x_dplls; 754 *ctrl = &dra7xx_ctrl; 755 break; 756 757 case DRA752_ES1_0: 758 case DRA752_ES1_1: 759 case DRA752_ES2_0: 760 *prcm = &dra7xx_prcm; 761 *dplls_data = &dra7xx_dplls; 762 *ctrl = &dra7xx_ctrl; 763 break; 764 765 case DRA722_ES1_0: 766 case DRA722_ES2_0: 767 case DRA722_ES2_1: 768 *prcm = &dra7xx_prcm; 769 *dplls_data = &dra72x_dplls; 770 *ctrl = &dra7xx_ctrl; 771 break; 772 773 default: 774 printf("\n INVALID OMAP REVISION "); 775 } 776 } 777 778 void get_ioregs(const struct ctrl_ioregs **regs) 779 { 780 u32 omap_rev = omap_revision(); 781 782 switch (omap_rev) { 783 case OMAP5430_ES1_0: 784 case OMAP5430_ES2_0: 785 *regs = &ioregs_omap5430; 786 break; 787 case OMAP5432_ES1_0: 788 *regs = &ioregs_omap5432_es1; 789 break; 790 case OMAP5432_ES2_0: 791 *regs = &ioregs_omap5432_es2; 792 break; 793 case DRA752_ES1_0: 794 case DRA752_ES1_1: 795 case DRA752_ES2_0: 796 case DRA762_ES1_0: 797 case DRA762_ACD_ES1_0: 798 case DRA762_ABZ_ES1_0: 799 *regs = &ioregs_dra7xx_es1; 800 break; 801 case DRA722_ES1_0: 802 *regs = &ioregs_dra72x_es1; 803 break; 804 case DRA722_ES2_0: 805 case DRA722_ES2_1: 806 *regs = &ioregs_dra72x_es2; 807 break; 808 809 default: 810 printf("\n INVALID OMAP REVISION "); 811 } 812 } 813