1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *
4  * HW data initialization for OMAP5
5  *
6  * (C) Copyright 2013
7  * Texas Instruments, <www.ti.com>
8  *
9  * Sricharan R <r.sricharan@ti.com>
10  */
11 #include <common.h>
12 #include <palmas.h>
13 #include <asm/arch/omap.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/omap_common.h>
16 #include <asm/arch/clock.h>
17 #include <asm/omap_gpio.h>
18 #include <asm/io.h>
19 #include <asm/emif.h>
20 
21 struct prcm_regs const **prcm =
22 			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
23 struct dplls const **dplls_data =
24 			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
25 struct vcores_data const **omap_vcores =
26 		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
27 struct omap_sys_ctrl_regs const **ctrl =
28 	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
29 
30 /* OPP NOM FREQUENCY for ES1.0 */
31 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
32 	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
33 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
34 	{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
35 	{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
36 	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
37 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
38 	{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
39 };
40 
41 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
42 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
43 	{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
44 	{500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
45 	{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
46 	{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
47 	{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
48 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
49 	{625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
50 };
51 
52 static const struct dpll_params
53 			core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
54 	{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 12 MHz   */
55 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
56 	{443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 16.8 MHz */
57 	{277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 19.2 MHz */
58 	{368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1},		/* 26 MHz   */
59 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
60 	{277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}		/* 38.4 MHz */
61 };
62 
63 static const struct dpll_params
64 			core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
65 	{266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 12 MHz   */
66 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
67 	{443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 16.8 MHz */
68 	{277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 19.2 MHz */
69 	{368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6},		/* 26 MHz   */
70 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
71 	{277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}		/* 38.4 MHz */
72 };
73 
74 static const struct dpll_params
75 		core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
76 	{266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 12 MHz   */
77 	{266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 20 MHz   */
78 	{443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 16.8 MHz */
79 	{277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 19.2 MHz */
80 	{368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 26 MHz   */
81 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
82 	{277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6},		/* 38.4 MHz */
83 };
84 
85 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
86 	{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
87 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
88 	{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
89 	{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
90 	{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
91 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
92 	{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
93 };
94 
95 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
96 	{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 12 MHz   */
97 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
98 	{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 16.8 MHz */
99 	{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 19.2 MHz */
100 	{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1},		/* 26 MHz   */
101 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
102 	{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}		/* 38.4 MHz */
103 };
104 
105 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
106 	{32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 12 MHz   */
107 	{96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1},		/* 20 MHz   */
108 	{160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 16.8 MHz */
109 	{20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 19.2 MHz */
110 	{192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 26 MHz   */
111 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
112 	{10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1},		/* 38.4 MHz */
113 };
114 
115 static const struct dpll_params per_dpll_params_768mhz_dra76x[NUM_SYS_CLKS] = {
116 	{32, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 12 MHz   */
117 	{96, 4, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 20 MHz   */
118 	{160, 6, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 16.8 MHz */
119 	{20, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 19.2 MHz */
120 	{192, 12, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 26 MHz   */
121 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
122 	{10, 0, 4, 1, 3, 4, 8, 2, -1, -1, -1, -1},		/* 38.4 MHz */
123 };
124 
125 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
126 	{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
127 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
128 	{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
129 	{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
130 	{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
131 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
132 	{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
133 };
134 
135 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
136 	{1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
137 	{233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz */
138 	{208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
139 	{182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
140 	{224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
141 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
142 	{91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
143 };
144 
145 /* ABE M & N values with sys_clk as source */
146 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
147 static const struct dpll_params
148 		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
149 	{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
150 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
151 	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
152 	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
153 	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
154 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
155 	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
156 };
157 #endif
158 
159 /* ABE M & N values with 32K clock as source */
160 #ifndef CONFIG_SYS_OMAP_ABE_SYSCK
161 static const struct dpll_params abe_dpll_params_32k_196608khz = {
162 	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
163 };
164 #endif
165 
166 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
167 static const struct dpll_params
168 		abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
169 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
170 	{16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
171 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
172 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
173 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
174 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
175 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
176 };
177 
178 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
179 	{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
180 	{480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 20 MHz   */
181 	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
182 	{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
183 	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
184 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
185 	{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 38.4 MHz */
186 };
187 
188 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = {
189 	{111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
190 	{333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
191 	{555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
192 	{555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
193 	{666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
194 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
195 	{555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
196 };
197 
198 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
199 	{266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
200 	{266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 20 MHz   */
201 	{190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 16.8 MHz */
202 	{665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
203 	{532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 26 MHz   */
204 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
205 	{665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1},		/* 38.4 MHz */
206 };
207 
208 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
209 	{250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 12 MHz   */
210 	{250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 20 MHz   */
211 	{119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},		/* 16.8 MHz */
212 	{625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 19.2 MHz */
213 	{500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 26 MHz   */
214 	{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
215 	{625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1},	/* 38.4 MHz */
216 };
217 
218 struct dplls omap5_dplls_es1 = {
219 	.mpu = mpu_dpll_params_800mhz,
220 	.core = core_dpll_params_2128mhz_ddr532,
221 	.per = per_dpll_params_768mhz,
222 	.iva = iva_dpll_params_2330mhz,
223 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
224 	.abe = abe_dpll_params_sysclk_196608khz,
225 #else
226 	.abe = &abe_dpll_params_32k_196608khz,
227 #endif
228 	.usb = usb_dpll_params_1920mhz,
229 	.ddr = NULL
230 };
231 
232 struct dplls omap5_dplls_es2 = {
233 	.mpu = mpu_dpll_params_1ghz,
234 	.core = core_dpll_params_2128mhz_ddr532_es2,
235 	.per = per_dpll_params_768mhz_es2,
236 	.iva = iva_dpll_params_2330mhz,
237 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
238 	.abe = abe_dpll_params_sysclk_196608khz,
239 #else
240 	.abe = &abe_dpll_params_32k_196608khz,
241 #endif
242 	.usb = usb_dpll_params_1920mhz,
243 	.ddr = NULL
244 };
245 
246 struct dplls dra76x_dplls = {
247 	.mpu = mpu_dpll_params_1ghz,
248 	.core = core_dpll_params_2128mhz_dra7xx,
249 	.per = per_dpll_params_768mhz_dra76x,
250 	.abe = abe_dpll_params_sysclk2_361267khz,
251 	.iva = iva_dpll_params_2330mhz_dra7xx,
252 	.usb = usb_dpll_params_1920mhz,
253 	.ddr =	ddr_dpll_params_2664mhz,
254 	.gmac = gmac_dpll_params_2000mhz,
255 };
256 
257 struct dplls dra7xx_dplls = {
258 	.mpu = mpu_dpll_params_1ghz,
259 	.core = core_dpll_params_2128mhz_dra7xx,
260 	.per = per_dpll_params_768mhz_dra7xx,
261 	.abe = abe_dpll_params_sysclk2_361267khz,
262 	.iva = iva_dpll_params_2330mhz_dra7xx,
263 	.usb = usb_dpll_params_1920mhz,
264 	.ddr = ddr_dpll_params_2128mhz,
265 	.gmac = gmac_dpll_params_2000mhz,
266 };
267 
268 struct dplls dra72x_dplls = {
269 	.mpu = mpu_dpll_params_1ghz,
270 	.core = core_dpll_params_2128mhz_dra7xx,
271 	.per = per_dpll_params_768mhz_dra7xx,
272 	.abe = abe_dpll_params_sysclk2_361267khz,
273 	.iva = iva_dpll_params_2330mhz_dra7xx,
274 	.usb = usb_dpll_params_1920mhz,
275 	.ddr =	ddr_dpll_params_2664mhz,
276 	.gmac = gmac_dpll_params_2000mhz,
277 };
278 
279 struct pmic_data palmas = {
280 	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
281 	.step = 10000, /* 10 mV represented in uV */
282 	/*
283 	 * Offset codes 1-6 all give the base voltage in Palmas
284 	 * Offset code 0 switches OFF the SMPS
285 	 */
286 	.start_code = 6,
287 	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
288 	.pmic_bus_init	= sri2c_init,
289 	.pmic_write	= omap_vc_bypass_send_value,
290 	.gpio_en = 0,
291 };
292 
293 /* The TPS659038 and TPS65917 are software-compatible, use common struct */
294 struct pmic_data tps659038 = {
295 	.base_offset = PALMAS_SMPS_BASE_VOLT_UV,
296 	.step = 10000, /* 10 mV represented in uV */
297 	/*
298 	 * Offset codes 1-6 all give the base voltage in Palmas
299 	 * Offset code 0 switches OFF the SMPS
300 	 */
301 	.start_code = 6,
302 	.i2c_slave_addr	= TPS659038_I2C_SLAVE_ADDR,
303 	.pmic_bus_init	= gpi2c_init,
304 	.pmic_write	= palmas_i2c_write_u8,
305 	.gpio_en = 0,
306 };
307 
308 /* The LP87565*/
309 struct pmic_data lp87565 = {
310 	.base_offset = LP873X_BUCK_BASE_VOLT_UV,
311 	.step = 5000, /* 5 mV represented in uV */
312 	/*
313 	 * Offset codes 0 - 0x13 Invalid.
314 	 * Offset codes 0x14 0x17 give 10mV steps
315 	 * Offset codes 0x17 through 0x9D give 5mV steps
316 	 * So let us start with our operating range from .73V
317 	 */
318 	.start_code = 0x17,
319 	.i2c_slave_addr = 0x60,
320 	.pmic_bus_init  = gpi2c_init,
321 	.pmic_write     = palmas_i2c_write_u8,
322 };
323 
324 /* The LP8732 and LP8733 are software-compatible, use common struct */
325 struct pmic_data lp8733 = {
326 	.base_offset = LP873X_BUCK_BASE_VOLT_UV,
327 	.step = 5000, /* 5 mV represented in uV */
328 	/*
329 	 * Offset codes 0 - 0x13 Invalid.
330 	 * Offset codes 0x14 0x17 give 10mV steps
331 	 * Offset codes 0x17 through 0x9D give 5mV steps
332 	 * So let us start with our operating range from .73V
333 	 */
334 	.start_code = 0x17,
335 	.i2c_slave_addr = 0x60,
336 	.pmic_bus_init  = gpi2c_init,
337 	.pmic_write     = palmas_i2c_write_u8,
338 };
339 
340 struct vcores_data omap5430_volts = {
341 	.mpu.value[OPP_NOM] = VDD_MPU,
342 	.mpu.addr = SMPS_REG_ADDR_12_MPU,
343 	.mpu.pmic = &palmas,
344 
345 	.core.value[OPP_NOM] = VDD_CORE,
346 	.core.addr = SMPS_REG_ADDR_8_CORE,
347 	.core.pmic = &palmas,
348 
349 	.mm.value[OPP_NOM] = VDD_MM,
350 	.mm.addr = SMPS_REG_ADDR_45_IVA,
351 	.mm.pmic = &palmas,
352 };
353 
354 struct vcores_data omap5430_volts_es2 = {
355 	.mpu.value[OPP_NOM] = VDD_MPU_ES2,
356 	.mpu.addr = SMPS_REG_ADDR_12_MPU,
357 	.mpu.pmic = &palmas,
358 	.mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
359 
360 	.core.value[OPP_NOM] = VDD_CORE_ES2,
361 	.core.addr = SMPS_REG_ADDR_8_CORE,
362 	.core.pmic = &palmas,
363 
364 	.mm.value[OPP_NOM] = VDD_MM_ES2,
365 	.mm.addr = SMPS_REG_ADDR_45_IVA,
366 	.mm.pmic = &palmas,
367 	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
368 
369 	.mpu.efuse.reg[OPP_NOM]	= OMAP5_ES2_PROD_MPU_OPNO_VMIN,
370 	.mpu.efuse.reg_bits	= OMAP5_ES2_PROD_REGBITS,
371 
372 	.core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN,
373 	.core.efuse.reg_bits	= OMAP5_ES2_PROD_REGBITS,
374 
375 	.mm.efuse.reg[OPP_NOM]	= OMAP5_ES2_PROD_MM_OPNO_VMIN,
376 	.mm.efuse.reg_bits	= OMAP5_ES2_PROD_REGBITS,
377 };
378 
379 /*
380  * Enable essential clock domains, modules and
381  * do some additional special settings needed
382  */
383 void enable_basic_clocks(void)
384 {
385 	u32 const clk_domains_essential[] = {
386 		(*prcm)->cm_l4per_clkstctrl,
387 		(*prcm)->cm_l3init_clkstctrl,
388 		(*prcm)->cm_memif_clkstctrl,
389 		(*prcm)->cm_l4cfg_clkstctrl,
390 #ifdef CONFIG_DRIVER_TI_CPSW
391 		(*prcm)->cm_gmac_clkstctrl,
392 #endif
393 		0
394 	};
395 
396 	u32 const clk_modules_hw_auto_essential[] = {
397 		(*prcm)->cm_l3_gpmc_clkctrl,
398 		(*prcm)->cm_memif_emif_1_clkctrl,
399 		(*prcm)->cm_memif_emif_2_clkctrl,
400 		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
401 		(*prcm)->cm_wkup_gpio1_clkctrl,
402 		(*prcm)->cm_l4per_gpio2_clkctrl,
403 		(*prcm)->cm_l4per_gpio3_clkctrl,
404 		(*prcm)->cm_l4per_gpio4_clkctrl,
405 		(*prcm)->cm_l4per_gpio5_clkctrl,
406 		(*prcm)->cm_l4per_gpio6_clkctrl,
407 		(*prcm)->cm_l4per_gpio7_clkctrl,
408 		(*prcm)->cm_l4per_gpio8_clkctrl,
409 #ifdef CONFIG_SCSI_AHCI_PLAT
410 		(*prcm)->cm_l3init_ocp2scp3_clkctrl,
411 #endif
412 		0
413 	};
414 
415 	u32 const clk_modules_explicit_en_essential[] = {
416 		(*prcm)->cm_wkup_gptimer1_clkctrl,
417 		(*prcm)->cm_l3init_hsmmc1_clkctrl,
418 		(*prcm)->cm_l3init_hsmmc2_clkctrl,
419 		(*prcm)->cm_l4per_gptimer2_clkctrl,
420 		(*prcm)->cm_wkup_wdtimer2_clkctrl,
421 		(*prcm)->cm_l4per_uart3_clkctrl,
422 		(*prcm)->cm_l4per_i2c1_clkctrl,
423 #ifdef CONFIG_DRIVER_TI_CPSW
424 		(*prcm)->cm_gmac_gmac_clkctrl,
425 #endif
426 
427 #ifdef CONFIG_TI_QSPI
428 		(*prcm)->cm_l4per_qspi_clkctrl,
429 #endif
430 #ifdef CONFIG_SCSI_AHCI_PLAT
431 		(*prcm)->cm_l3init_sata_clkctrl,
432 #endif
433 		0
434 	};
435 
436 	/* Enable optional additional functional clock for GPIO4 */
437 	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
438 			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
439 
440 	/* Enable 192 MHz clock for MMC1 & MMC2 */
441 	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
442 			HSMMC_CLKCTRL_CLKSEL_MASK);
443 	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
444 			HSMMC_CLKCTRL_CLKSEL_MASK);
445 
446 	/* Set the correct clock dividers for mmc */
447 	clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
448 		     HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
449 	clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
450 		     HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
451 
452 	/* Select 32KHz clock as the source of GPTIMER1 */
453 	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
454 			GPTIMER1_CLKCTRL_CLKSEL_MASK);
455 
456 	do_enable_clocks(clk_domains_essential,
457 			 clk_modules_hw_auto_essential,
458 			 clk_modules_explicit_en_essential,
459 			 1);
460 
461 #ifdef CONFIG_TI_QSPI
462 	setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
463 #endif
464 
465 #ifdef CONFIG_SCSI_AHCI_PLAT
466 	/* Enable optional functional clock for SATA */
467 	setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
468 		     SATA_CLKCTRL_OPTFCLKEN_MASK);
469 #endif
470 
471 	/* Enable SCRM OPT clocks for PER and CORE dpll */
472 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
473 			OPTFCLKEN_SCRM_PER_MASK);
474 	setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
475 			OPTFCLKEN_SCRM_CORE_MASK);
476 }
477 
478 void enable_basic_uboot_clocks(void)
479 {
480 	u32 const clk_domains_essential[] = {
481 #if defined(CONFIG_DRA7XX)
482 		(*prcm)->cm_ipu_clkstctrl,
483 #endif
484 		0
485 	};
486 
487 	u32 const clk_modules_hw_auto_essential[] = {
488 		(*prcm)->cm_l3init_hsusbtll_clkctrl,
489 		0
490 	};
491 
492 	u32 const clk_modules_explicit_en_essential[] = {
493 		(*prcm)->cm_l4per_mcspi1_clkctrl,
494 		(*prcm)->cm_l4per_i2c2_clkctrl,
495 		(*prcm)->cm_l4per_i2c3_clkctrl,
496 		(*prcm)->cm_l4per_i2c4_clkctrl,
497 #if defined(CONFIG_DRA7XX)
498 		(*prcm)->cm_ipu_i2c5_clkctrl,
499 #else
500 		(*prcm)->cm_l4per_i2c5_clkctrl,
501 #endif
502 		(*prcm)->cm_l3init_hsusbhost_clkctrl,
503 		(*prcm)->cm_l3init_fsusb_clkctrl,
504 		0
505 	};
506 	do_enable_clocks(clk_domains_essential,
507 			 clk_modules_hw_auto_essential,
508 			 clk_modules_explicit_en_essential,
509 			 1);
510 }
511 
512 #ifdef CONFIG_TI_EDMA3
513 void enable_edma3_clocks(void)
514 {
515 	u32 const clk_domains_edma3[] = {
516 		0
517 	};
518 
519 	u32 const clk_modules_hw_auto_edma3[] = {
520 		(*prcm)->cm_l3main1_tptc1_clkctrl,
521 		(*prcm)->cm_l3main1_tptc2_clkctrl,
522 		0
523 	};
524 
525 	u32 const clk_modules_explicit_en_edma3[] = {
526 		0
527 	};
528 
529 	do_enable_clocks(clk_domains_edma3,
530 			 clk_modules_hw_auto_edma3,
531 			 clk_modules_explicit_en_edma3,
532 			 1);
533 }
534 
535 void disable_edma3_clocks(void)
536 {
537 	u32 const clk_domains_edma3[] = {
538 		0
539 	};
540 
541 	u32 const clk_modules_disable_edma3[] = {
542 		(*prcm)->cm_l3main1_tptc1_clkctrl,
543 		(*prcm)->cm_l3main1_tptc2_clkctrl,
544 		0
545 	};
546 
547 	do_disable_clocks(clk_domains_edma3,
548 			  clk_modules_disable_edma3,
549 			  1);
550 }
551 #endif
552 
553 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
554 void enable_usb_clocks(int index)
555 {
556 	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
557 
558 	if (index == 0) {
559 		cm_l3init_usb_otg_ss_clkctrl =
560 			(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
561 		/* Enable 960 MHz clock for dwc3 */
562 		setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
563 			     OPTFCLKEN_REFCLK960M);
564 
565 		/* Enable 32 KHz clock for USB_PHY1 */
566 		setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
567 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
568 
569 		/* Enable 32 KHz clock for USB_PHY3 */
570 		if (is_dra7xx())
571 			setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
572 				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
573 	} else if (index == 1) {
574 		cm_l3init_usb_otg_ss_clkctrl =
575 			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
576 		/* Enable 960 MHz clock for dwc3 */
577 		setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
578 			     OPTFCLKEN_REFCLK960M);
579 
580 		/* Enable 32 KHz clock for dwc3 */
581 		setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
582 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
583 
584 		/* Enable 60 MHz clock for USB2PHY2 */
585 		setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
586 			     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
587 	}
588 
589 	u32 const clk_domains_usb[] = {
590 		0
591 	};
592 
593 	u32 const clk_modules_hw_auto_usb[] = {
594 		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
595 		cm_l3init_usb_otg_ss_clkctrl,
596 		0
597 	};
598 
599 	u32 const clk_modules_explicit_en_usb[] = {
600 		0
601 	};
602 
603 	do_enable_clocks(clk_domains_usb,
604 			 clk_modules_hw_auto_usb,
605 			 clk_modules_explicit_en_usb,
606 			 1);
607 }
608 
609 void disable_usb_clocks(int index)
610 {
611 	u32 cm_l3init_usb_otg_ss_clkctrl = 0;
612 
613 	if (index == 0) {
614 		cm_l3init_usb_otg_ss_clkctrl =
615 			(*prcm)->cm_l3init_usb_otg_ss1_clkctrl;
616 		/* Disable 960 MHz clock for dwc3 */
617 		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
618 			     OPTFCLKEN_REFCLK960M);
619 
620 		/* Disable 32 KHz clock for USB_PHY1 */
621 		clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
622 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
623 
624 		/* Disable 32 KHz clock for USB_PHY3 */
625 		if (is_dra7xx())
626 			clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl,
627 				     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
628 	} else if (index == 1) {
629 		cm_l3init_usb_otg_ss_clkctrl =
630 			(*prcm)->cm_l3init_usb_otg_ss2_clkctrl;
631 		/* Disable 960 MHz clock for dwc3 */
632 		clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
633 			     OPTFCLKEN_REFCLK960M);
634 
635 		/* Disable 32 KHz clock for dwc3 */
636 		clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
637 			     USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
638 
639 		/* Disable 60 MHz clock for USB2PHY2 */
640 		clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
641 			     L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
642 	}
643 
644 	u32 const clk_domains_usb[] = {
645 		0
646 	};
647 
648 	u32 const clk_modules_disable[] = {
649 		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
650 		cm_l3init_usb_otg_ss_clkctrl,
651 		0
652 	};
653 
654 	do_disable_clocks(clk_domains_usb,
655 			  clk_modules_disable,
656 			  1);
657 }
658 #endif
659 
660 const struct ctrl_ioregs ioregs_omap5430 = {
661 	.ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
662 	.ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
663 	.ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
664 	.ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
665 	.ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
666 };
667 
668 const struct ctrl_ioregs ioregs_omap5432_es1 = {
669 	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
670 	.ctrl_lpddr2ch = 0x0,
671 	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
672 	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
673 	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
674 	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
675 	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
676 	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
677 };
678 
679 const struct ctrl_ioregs ioregs_omap5432_es2 = {
680 	.ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
681 	.ctrl_lpddr2ch = 0x0,
682 	.ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
683 	.ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
684 	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
685 	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
686 	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
687 	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
688 };
689 
690 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
691 	.ctrl_ddrch = 0x40404040,
692 	.ctrl_lpddr2ch = 0x40404040,
693 	.ctrl_ddr3ch = 0x80808080,
694 	.ctrl_ddrio_0 = 0x00094A40,
695 	.ctrl_ddrio_1 = 0x04A52000,
696 	.ctrl_ddrio_2 = 0x84210000,
697 	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
698 	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
699 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
700 };
701 
702 const struct ctrl_ioregs ioregs_dra72x_es1 = {
703 	.ctrl_ddrch = 0x40404040,
704 	.ctrl_lpddr2ch = 0x40404040,
705 	.ctrl_ddr3ch = 0x60606080,
706 	.ctrl_ddrio_0 = 0x00094A40,
707 	.ctrl_ddrio_1 = 0x04A52000,
708 	.ctrl_ddrio_2 = 0x84210000,
709 	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
710 	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
711 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
712 };
713 
714 const struct ctrl_ioregs ioregs_dra72x_es2 = {
715 	.ctrl_ddrch = 0x40404040,
716 	.ctrl_lpddr2ch = 0x40404040,
717 	.ctrl_ddr3ch = 0x60606060,
718 	.ctrl_ddrio_0 = 0x00094A40,
719 	.ctrl_ddrio_1 = 0x00000000,
720 	.ctrl_ddrio_2 = 0x00000000,
721 	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
722 	.ctrl_emif_sdram_config_ext_final = 0x0001C1A7,
723 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
724 };
725 
726 void __weak hw_data_init(void)
727 {
728 	u32 omap_rev = omap_revision();
729 
730 	switch (omap_rev) {
731 
732 	case OMAP5430_ES1_0:
733 	case OMAP5432_ES1_0:
734 	*prcm = &omap5_es1_prcm;
735 	*dplls_data = &omap5_dplls_es1;
736 	*omap_vcores = &omap5430_volts;
737 	*ctrl = &omap5_ctrl;
738 	break;
739 
740 	case OMAP5430_ES2_0:
741 	case OMAP5432_ES2_0:
742 	*prcm = &omap5_es2_prcm;
743 	*dplls_data = &omap5_dplls_es2;
744 	*omap_vcores = &omap5430_volts_es2;
745 	*ctrl = &omap5_ctrl;
746 	break;
747 
748 	case DRA762_ABZ_ES1_0:
749 	case DRA762_ACD_ES1_0:
750 	case DRA762_ES1_0:
751 	*prcm = &dra7xx_prcm;
752 	*dplls_data = &dra76x_dplls;
753 	*ctrl = &dra7xx_ctrl;
754 	break;
755 
756 	case DRA752_ES1_0:
757 	case DRA752_ES1_1:
758 	case DRA752_ES2_0:
759 	*prcm = &dra7xx_prcm;
760 	*dplls_data = &dra7xx_dplls;
761 	*ctrl = &dra7xx_ctrl;
762 	break;
763 
764 	case DRA722_ES1_0:
765 	case DRA722_ES2_0:
766 	case DRA722_ES2_1:
767 	*prcm = &dra7xx_prcm;
768 	*dplls_data = &dra72x_dplls;
769 	*ctrl = &dra7xx_ctrl;
770 	break;
771 
772 	default:
773 		printf("\n INVALID OMAP REVISION ");
774 	}
775 }
776 
777 void get_ioregs(const struct ctrl_ioregs **regs)
778 {
779 	u32 omap_rev = omap_revision();
780 
781 	switch (omap_rev) {
782 	case OMAP5430_ES1_0:
783 	case OMAP5430_ES2_0:
784 		*regs = &ioregs_omap5430;
785 		break;
786 	case OMAP5432_ES1_0:
787 		*regs = &ioregs_omap5432_es1;
788 		break;
789 	case OMAP5432_ES2_0:
790 		*regs = &ioregs_omap5432_es2;
791 		break;
792 	case DRA752_ES1_0:
793 	case DRA752_ES1_1:
794 	case DRA752_ES2_0:
795 	case DRA762_ES1_0:
796 	case DRA762_ACD_ES1_0:
797 	case DRA762_ABZ_ES1_0:
798 		*regs = &ioregs_dra7xx_es1;
799 		break;
800 	case DRA722_ES1_0:
801 		*regs = &ioregs_dra72x_es1;
802 		break;
803 	case DRA722_ES2_0:
804 	case DRA722_ES2_1:
805 		*regs = &ioregs_dra72x_es2;
806 		break;
807 
808 	default:
809 		printf("\n INVALID OMAP REVISION ");
810 	}
811 }
812