1 /* 2 * 3 * HW data initialization for OMAP5 4 * 5 * (C) Copyright 2013 6 * Texas Instruments, <www.ti.com> 7 * 8 * Sricharan R <r.sricharan@ti.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #include <common.h> 13 #include <palmas.h> 14 #include <asm/arch/omap.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/omap_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/omap_gpio.h> 19 #include <asm/io.h> 20 #include <asm/emif.h> 21 22 struct prcm_regs const **prcm = 23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; 24 struct dplls const **dplls_data = 25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; 26 struct vcores_data const **omap_vcores = 27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; 28 struct omap_sys_ctrl_regs const **ctrl = 29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; 30 31 /* OPP HIGH FREQUENCY for ES2.0 */ 32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { 33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 40 }; 41 42 /* OPP NOM FREQUENCY for ES1.0 */ 43 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { 44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 51 }; 52 53 /* OPP LOW FREQUENCY for ES1.0 */ 54 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { 55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 62 }; 63 64 /* OPP LOW FREQUENCY for ES2.0 */ 65 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { 66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 73 }; 74 75 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ 76 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { 77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 84 }; 85 86 static const struct dpll_params 87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { 88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ 89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ 91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ 92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ 93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ 95 }; 96 97 static const struct dpll_params 98 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { 99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ 100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ 102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ 103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ 104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ 106 }; 107 108 static const struct dpll_params 109 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { 110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ 111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ 112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ 113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ 114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ 115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ 117 }; 118 119 static const struct dpll_params 120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { 121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ 122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ 124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ 125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ 126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ 128 }; 129 130 static const struct dpll_params 131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { 132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ 133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ 135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ 136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ 137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ 139 }; 140 141 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { 142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 149 }; 150 151 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { 152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 159 }; 160 161 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { 162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ 163 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ 164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ 167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 169 }; 170 171 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { 172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 179 }; 180 181 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { 182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 189 }; 190 191 /* ABE M & N values with sys_clk as source */ 192 static const struct dpll_params 193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { 194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 201 }; 202 203 /* ABE M & N values with 32K clock as source */ 204 static const struct dpll_params abe_dpll_params_32k_196608khz = { 205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 206 }; 207 208 /* ABE M & N values with sysclk2(22.5792 MHz) as input */ 209 static const struct dpll_params 210 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { 211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 218 }; 219 220 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { 221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 228 }; 229 230 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { 231 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 232 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 233 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 234 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 235 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 237 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 238 }; 239 240 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { 241 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 242 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 243 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 244 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 245 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 247 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 248 }; 249 250 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { 251 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ 252 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ 253 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 254 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 255 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ 256 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 257 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 258 }; 259 260 struct dplls omap5_dplls_es1 = { 261 .mpu = mpu_dpll_params_800mhz, 262 .core = core_dpll_params_2128mhz_ddr532, 263 .per = per_dpll_params_768mhz, 264 .iva = iva_dpll_params_2330mhz, 265 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 266 .abe = abe_dpll_params_sysclk_196608khz, 267 #else 268 .abe = &abe_dpll_params_32k_196608khz, 269 #endif 270 .usb = usb_dpll_params_1920mhz, 271 .ddr = NULL 272 }; 273 274 struct dplls omap5_dplls_es2 = { 275 .mpu = mpu_dpll_params_1ghz, 276 .core = core_dpll_params_2128mhz_ddr532_es2, 277 .per = per_dpll_params_768mhz_es2, 278 .iva = iva_dpll_params_2330mhz, 279 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 280 .abe = abe_dpll_params_sysclk_196608khz, 281 #else 282 .abe = &abe_dpll_params_32k_196608khz, 283 #endif 284 .usb = usb_dpll_params_1920mhz, 285 .ddr = NULL 286 }; 287 288 struct dplls dra7xx_dplls = { 289 .mpu = mpu_dpll_params_1ghz, 290 .core = core_dpll_params_2128mhz_dra7xx, 291 .per = per_dpll_params_768mhz_dra7xx, 292 .abe = abe_dpll_params_sysclk2_361267khz, 293 .iva = iva_dpll_params_2330mhz_dra7xx, 294 .usb = usb_dpll_params_1920mhz, 295 .ddr = ddr_dpll_params_2128mhz, 296 .gmac = gmac_dpll_params_2000mhz, 297 }; 298 299 struct dplls dra72x_dplls = { 300 .mpu = mpu_dpll_params_1ghz, 301 .core = core_dpll_params_2128mhz_dra7xx, 302 .per = per_dpll_params_768mhz_dra7xx, 303 .abe = abe_dpll_params_sysclk2_361267khz, 304 .iva = iva_dpll_params_2330mhz_dra7xx, 305 .usb = usb_dpll_params_1920mhz, 306 .ddr = ddr_dpll_params_2664mhz, 307 .gmac = gmac_dpll_params_2000mhz, 308 }; 309 310 struct pmic_data palmas = { 311 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 312 .step = 10000, /* 10 mV represented in uV */ 313 /* 314 * Offset codes 1-6 all give the base voltage in Palmas 315 * Offset code 0 switches OFF the SMPS 316 */ 317 .start_code = 6, 318 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, 319 .pmic_bus_init = sri2c_init, 320 .pmic_write = omap_vc_bypass_send_value, 321 .gpio_en = 0, 322 }; 323 324 /* The TPS659038 and TPS65917 are software-compatible, use common struct */ 325 struct pmic_data tps659038 = { 326 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 327 .step = 10000, /* 10 mV represented in uV */ 328 /* 329 * Offset codes 1-6 all give the base voltage in Palmas 330 * Offset code 0 switches OFF the SMPS 331 */ 332 .start_code = 6, 333 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, 334 .pmic_bus_init = gpi2c_init, 335 .pmic_write = palmas_i2c_write_u8, 336 .gpio_en = 0, 337 }; 338 339 struct vcores_data omap5430_volts = { 340 .mpu.value = VDD_MPU, 341 .mpu.addr = SMPS_REG_ADDR_12_MPU, 342 .mpu.pmic = &palmas, 343 344 .core.value = VDD_CORE, 345 .core.addr = SMPS_REG_ADDR_8_CORE, 346 .core.pmic = &palmas, 347 348 .mm.value = VDD_MM, 349 .mm.addr = SMPS_REG_ADDR_45_IVA, 350 .mm.pmic = &palmas, 351 }; 352 353 struct vcores_data omap5430_volts_es2 = { 354 .mpu.value = VDD_MPU_ES2, 355 .mpu.addr = SMPS_REG_ADDR_12_MPU, 356 .mpu.pmic = &palmas, 357 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 358 359 .core.value = VDD_CORE_ES2, 360 .core.addr = SMPS_REG_ADDR_8_CORE, 361 .core.pmic = &palmas, 362 363 .mm.value = VDD_MM_ES2, 364 .mm.addr = SMPS_REG_ADDR_45_IVA, 365 .mm.pmic = &palmas, 366 .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, 367 }; 368 369 /* 370 * Enable essential clock domains, modules and 371 * do some additional special settings needed 372 */ 373 void enable_basic_clocks(void) 374 { 375 u32 const clk_domains_essential[] = { 376 (*prcm)->cm_l4per_clkstctrl, 377 (*prcm)->cm_l3init_clkstctrl, 378 (*prcm)->cm_memif_clkstctrl, 379 (*prcm)->cm_l4cfg_clkstctrl, 380 #ifdef CONFIG_DRIVER_TI_CPSW 381 (*prcm)->cm_gmac_clkstctrl, 382 #endif 383 0 384 }; 385 386 u32 const clk_modules_hw_auto_essential[] = { 387 (*prcm)->cm_l3_gpmc_clkctrl, 388 (*prcm)->cm_memif_emif_1_clkctrl, 389 (*prcm)->cm_memif_emif_2_clkctrl, 390 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, 391 (*prcm)->cm_wkup_gpio1_clkctrl, 392 (*prcm)->cm_l4per_gpio2_clkctrl, 393 (*prcm)->cm_l4per_gpio3_clkctrl, 394 (*prcm)->cm_l4per_gpio4_clkctrl, 395 (*prcm)->cm_l4per_gpio5_clkctrl, 396 (*prcm)->cm_l4per_gpio6_clkctrl, 397 (*prcm)->cm_l4per_gpio7_clkctrl, 398 (*prcm)->cm_l4per_gpio8_clkctrl, 399 0 400 }; 401 402 u32 const clk_modules_explicit_en_essential[] = { 403 (*prcm)->cm_wkup_gptimer1_clkctrl, 404 (*prcm)->cm_l3init_hsmmc1_clkctrl, 405 (*prcm)->cm_l3init_hsmmc2_clkctrl, 406 (*prcm)->cm_l4per_gptimer2_clkctrl, 407 (*prcm)->cm_wkup_wdtimer2_clkctrl, 408 (*prcm)->cm_l4per_uart3_clkctrl, 409 (*prcm)->cm_l4per_i2c1_clkctrl, 410 #ifdef CONFIG_DRIVER_TI_CPSW 411 (*prcm)->cm_gmac_gmac_clkctrl, 412 #endif 413 414 #ifdef CONFIG_TI_QSPI 415 (*prcm)->cm_l4per_qspi_clkctrl, 416 #endif 417 0 418 }; 419 420 /* Enable optional additional functional clock for GPIO4 */ 421 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, 422 GPIO4_CLKCTRL_OPTFCLKEN_MASK); 423 424 /* Enable 96 MHz clock for MMC1 & MMC2 */ 425 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 426 HSMMC_CLKCTRL_CLKSEL_MASK); 427 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 428 HSMMC_CLKCTRL_CLKSEL_MASK); 429 430 /* Set the correct clock dividers for mmc */ 431 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 432 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 433 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 434 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 435 436 /* Select 32KHz clock as the source of GPTIMER1 */ 437 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, 438 GPTIMER1_CLKCTRL_CLKSEL_MASK); 439 440 do_enable_clocks(clk_domains_essential, 441 clk_modules_hw_auto_essential, 442 clk_modules_explicit_en_essential, 443 1); 444 445 #ifdef CONFIG_TI_QSPI 446 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); 447 #endif 448 449 /* Enable SCRM OPT clocks for PER and CORE dpll */ 450 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 451 OPTFCLKEN_SCRM_PER_MASK); 452 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 453 OPTFCLKEN_SCRM_CORE_MASK); 454 } 455 456 void enable_basic_uboot_clocks(void) 457 { 458 u32 const clk_domains_essential[] = { 459 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 460 (*prcm)->cm_ipu_clkstctrl, 461 #endif 462 0 463 }; 464 465 u32 const clk_modules_hw_auto_essential[] = { 466 (*prcm)->cm_l3init_hsusbtll_clkctrl, 467 0 468 }; 469 470 u32 const clk_modules_explicit_en_essential[] = { 471 (*prcm)->cm_l4per_mcspi1_clkctrl, 472 (*prcm)->cm_l4per_i2c2_clkctrl, 473 (*prcm)->cm_l4per_i2c3_clkctrl, 474 (*prcm)->cm_l4per_i2c4_clkctrl, 475 #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) 476 (*prcm)->cm_ipu_i2c5_clkctrl, 477 #else 478 (*prcm)->cm_l4per_i2c5_clkctrl, 479 #endif 480 (*prcm)->cm_l3init_hsusbhost_clkctrl, 481 (*prcm)->cm_l3init_fsusb_clkctrl, 482 0 483 }; 484 do_enable_clocks(clk_domains_essential, 485 clk_modules_hw_auto_essential, 486 clk_modules_explicit_en_essential, 487 1); 488 } 489 490 #ifdef CONFIG_TI_EDMA3 491 void enable_edma3_clocks(void) 492 { 493 u32 const clk_domains_edma3[] = { 494 0 495 }; 496 497 u32 const clk_modules_hw_auto_edma3[] = { 498 (*prcm)->cm_l3main1_tptc1_clkctrl, 499 (*prcm)->cm_l3main1_tptc2_clkctrl, 500 0 501 }; 502 503 u32 const clk_modules_explicit_en_edma3[] = { 504 0 505 }; 506 507 do_enable_clocks(clk_domains_edma3, 508 clk_modules_hw_auto_edma3, 509 clk_modules_explicit_en_edma3, 510 1); 511 } 512 513 void disable_edma3_clocks(void) 514 { 515 u32 const clk_domains_edma3[] = { 516 0 517 }; 518 519 u32 const clk_modules_disable_edma3[] = { 520 (*prcm)->cm_l3main1_tptc1_clkctrl, 521 (*prcm)->cm_l3main1_tptc2_clkctrl, 522 0 523 }; 524 525 do_disable_clocks(clk_domains_edma3, 526 clk_modules_disable_edma3, 527 1); 528 } 529 #endif 530 531 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 532 void enable_usb_clocks(int index) 533 { 534 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 535 536 if (index == 0) { 537 cm_l3init_usb_otg_ss_clkctrl = 538 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 539 /* Enable 960 MHz clock for dwc3 */ 540 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 541 OPTFCLKEN_REFCLK960M); 542 543 /* Enable 32 KHz clock for USB_PHY1 */ 544 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 545 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 546 547 /* Enable 32 KHz clock for USB_PHY3 */ 548 if (is_dra7xx()) 549 setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 550 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 551 } else if (index == 1) { 552 cm_l3init_usb_otg_ss_clkctrl = 553 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 554 /* Enable 960 MHz clock for dwc3 */ 555 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 556 OPTFCLKEN_REFCLK960M); 557 558 /* Enable 32 KHz clock for dwc3 */ 559 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 560 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 561 562 /* Enable 60 MHz clock for USB2PHY2 */ 563 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 564 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 565 } 566 567 u32 const clk_domains_usb[] = { 568 0 569 }; 570 571 u32 const clk_modules_hw_auto_usb[] = { 572 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 573 cm_l3init_usb_otg_ss_clkctrl, 574 0 575 }; 576 577 u32 const clk_modules_explicit_en_usb[] = { 578 0 579 }; 580 581 do_enable_clocks(clk_domains_usb, 582 clk_modules_hw_auto_usb, 583 clk_modules_explicit_en_usb, 584 1); 585 } 586 587 void disable_usb_clocks(int index) 588 { 589 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 590 591 if (index == 0) { 592 cm_l3init_usb_otg_ss_clkctrl = 593 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 594 /* Disable 960 MHz clock for dwc3 */ 595 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 596 OPTFCLKEN_REFCLK960M); 597 598 /* Disable 32 KHz clock for USB_PHY1 */ 599 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 600 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 601 602 /* Disable 32 KHz clock for USB_PHY3 */ 603 if (is_dra7xx()) 604 clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 605 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 606 } else if (index == 1) { 607 cm_l3init_usb_otg_ss_clkctrl = 608 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 609 /* Disable 960 MHz clock for dwc3 */ 610 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 611 OPTFCLKEN_REFCLK960M); 612 613 /* Disable 32 KHz clock for dwc3 */ 614 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 615 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 616 617 /* Disable 60 MHz clock for USB2PHY2 */ 618 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 619 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 620 } 621 622 u32 const clk_domains_usb[] = { 623 0 624 }; 625 626 u32 const clk_modules_disable[] = { 627 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 628 cm_l3init_usb_otg_ss_clkctrl, 629 0 630 }; 631 632 do_disable_clocks(clk_domains_usb, 633 clk_modules_disable, 634 1); 635 } 636 #endif 637 638 const struct ctrl_ioregs ioregs_omap5430 = { 639 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, 640 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, 641 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, 642 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, 643 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, 644 }; 645 646 const struct ctrl_ioregs ioregs_omap5432_es1 = { 647 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, 648 .ctrl_lpddr2ch = 0x0, 649 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, 650 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, 651 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, 652 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, 653 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 654 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 655 }; 656 657 const struct ctrl_ioregs ioregs_omap5432_es2 = { 658 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 659 .ctrl_lpddr2ch = 0x0, 660 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 661 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, 662 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, 663 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, 664 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 665 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 666 }; 667 668 const struct ctrl_ioregs ioregs_dra7xx_es1 = { 669 .ctrl_ddrch = 0x40404040, 670 .ctrl_lpddr2ch = 0x40404040, 671 .ctrl_ddr3ch = 0x80808080, 672 .ctrl_ddrio_0 = 0x00094A40, 673 .ctrl_ddrio_1 = 0x04A52000, 674 .ctrl_ddrio_2 = 0x84210000, 675 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 676 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 677 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 678 }; 679 680 const struct ctrl_ioregs ioregs_dra72x_es1 = { 681 .ctrl_ddrch = 0x40404040, 682 .ctrl_lpddr2ch = 0x40404040, 683 .ctrl_ddr3ch = 0x60606080, 684 .ctrl_ddrio_0 = 0x00094A40, 685 .ctrl_ddrio_1 = 0x04A52000, 686 .ctrl_ddrio_2 = 0x84210000, 687 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 688 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 689 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 690 }; 691 692 const struct ctrl_ioregs ioregs_dra72x_es2 = { 693 .ctrl_ddrch = 0x40404040, 694 .ctrl_lpddr2ch = 0x40404040, 695 .ctrl_ddr3ch = 0x60606060, 696 .ctrl_ddrio_0 = 0x00094A40, 697 .ctrl_ddrio_1 = 0x00000000, 698 .ctrl_ddrio_2 = 0x00000000, 699 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 700 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 701 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 702 }; 703 704 void __weak hw_data_init(void) 705 { 706 u32 omap_rev = omap_revision(); 707 708 switch (omap_rev) { 709 710 case OMAP5430_ES1_0: 711 case OMAP5432_ES1_0: 712 *prcm = &omap5_es1_prcm; 713 *dplls_data = &omap5_dplls_es1; 714 *omap_vcores = &omap5430_volts; 715 *ctrl = &omap5_ctrl; 716 break; 717 718 case OMAP5430_ES2_0: 719 case OMAP5432_ES2_0: 720 *prcm = &omap5_es2_prcm; 721 *dplls_data = &omap5_dplls_es2; 722 *omap_vcores = &omap5430_volts_es2; 723 *ctrl = &omap5_ctrl; 724 break; 725 726 case DRA752_ES1_0: 727 case DRA752_ES1_1: 728 case DRA752_ES2_0: 729 *prcm = &dra7xx_prcm; 730 *dplls_data = &dra7xx_dplls; 731 *ctrl = &dra7xx_ctrl; 732 break; 733 734 case DRA722_ES1_0: 735 case DRA722_ES2_0: 736 *prcm = &dra7xx_prcm; 737 *dplls_data = &dra72x_dplls; 738 *ctrl = &dra7xx_ctrl; 739 break; 740 741 default: 742 printf("\n INVALID OMAP REVISION "); 743 } 744 } 745 746 void get_ioregs(const struct ctrl_ioregs **regs) 747 { 748 u32 omap_rev = omap_revision(); 749 750 switch (omap_rev) { 751 case OMAP5430_ES1_0: 752 case OMAP5430_ES2_0: 753 *regs = &ioregs_omap5430; 754 break; 755 case OMAP5432_ES1_0: 756 *regs = &ioregs_omap5432_es1; 757 break; 758 case OMAP5432_ES2_0: 759 *regs = &ioregs_omap5432_es2; 760 break; 761 case DRA752_ES1_0: 762 case DRA752_ES1_1: 763 case DRA752_ES2_0: 764 *regs = &ioregs_dra7xx_es1; 765 break; 766 case DRA722_ES1_0: 767 *regs = &ioregs_dra72x_es1; 768 break; 769 case DRA722_ES2_0: 770 *regs = &ioregs_dra72x_es2; 771 break; 772 773 default: 774 printf("\n INVALID OMAP REVISION "); 775 } 776 } 777