1 /* 2 * 3 * HW data initialization for OMAP5 4 * 5 * (C) Copyright 2013 6 * Texas Instruments, <www.ti.com> 7 * 8 * Sricharan R <r.sricharan@ti.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #include <common.h> 13 #include <palmas.h> 14 #include <asm/arch/omap.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/omap_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/omap_gpio.h> 19 #include <asm/io.h> 20 #include <asm/emif.h> 21 22 struct prcm_regs const **prcm = 23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; 24 struct dplls const **dplls_data = 25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; 26 struct vcores_data const **omap_vcores = 27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; 28 struct omap_sys_ctrl_regs const **ctrl = 29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; 30 31 /* OPP NOM FREQUENCY for ES1.0 */ 32 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { 33 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 35 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 36 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 37 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 39 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 40 }; 41 42 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ 43 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { 44 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 45 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 46 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 47 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 48 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 50 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 51 }; 52 53 static const struct dpll_params 54 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { 55 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ 56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 57 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ 58 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ 59 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ 60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 61 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ 62 }; 63 64 static const struct dpll_params 65 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { 66 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ 67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 68 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ 69 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ 70 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ 71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 72 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ 73 }; 74 75 static const struct dpll_params 76 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { 77 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ 78 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ 79 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ 80 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ 81 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ 82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 83 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ 84 }; 85 86 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { 87 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 88 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 89 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 90 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 91 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 92 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 93 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 94 }; 95 96 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { 97 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 98 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 99 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 100 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 101 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 102 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 103 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 104 }; 105 106 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { 107 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ 108 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ 109 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 110 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 111 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ 112 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 113 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 114 }; 115 116 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { 117 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 118 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 119 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 120 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 121 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 123 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 124 }; 125 126 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { 127 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 128 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 129 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 130 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 131 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 132 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 133 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 134 }; 135 136 /* ABE M & N values with sys_clk as source */ 137 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 138 static const struct dpll_params 139 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { 140 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 142 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 143 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 144 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 145 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 146 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 147 }; 148 #endif 149 150 /* ABE M & N values with 32K clock as source */ 151 #ifndef CONFIG_SYS_OMAP_ABE_SYSCK 152 static const struct dpll_params abe_dpll_params_32k_196608khz = { 153 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 154 }; 155 #endif 156 157 /* ABE M & N values with sysclk2(22.5792 MHz) as input */ 158 static const struct dpll_params 159 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { 160 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 161 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 162 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 163 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 164 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 165 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 166 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 167 }; 168 169 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { 170 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 171 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 172 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 173 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 174 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 175 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 176 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 177 }; 178 179 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { 180 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 181 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 182 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 183 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 184 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 185 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 186 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 187 }; 188 189 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { 190 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 191 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 192 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 193 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 194 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 196 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 197 }; 198 199 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { 200 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ 201 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ 202 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 203 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 204 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ 205 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 206 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 207 }; 208 209 struct dplls omap5_dplls_es1 = { 210 .mpu = mpu_dpll_params_800mhz, 211 .core = core_dpll_params_2128mhz_ddr532, 212 .per = per_dpll_params_768mhz, 213 .iva = iva_dpll_params_2330mhz, 214 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 215 .abe = abe_dpll_params_sysclk_196608khz, 216 #else 217 .abe = &abe_dpll_params_32k_196608khz, 218 #endif 219 .usb = usb_dpll_params_1920mhz, 220 .ddr = NULL 221 }; 222 223 struct dplls omap5_dplls_es2 = { 224 .mpu = mpu_dpll_params_1ghz, 225 .core = core_dpll_params_2128mhz_ddr532_es2, 226 .per = per_dpll_params_768mhz_es2, 227 .iva = iva_dpll_params_2330mhz, 228 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 229 .abe = abe_dpll_params_sysclk_196608khz, 230 #else 231 .abe = &abe_dpll_params_32k_196608khz, 232 #endif 233 .usb = usb_dpll_params_1920mhz, 234 .ddr = NULL 235 }; 236 237 struct dplls dra7xx_dplls = { 238 .mpu = mpu_dpll_params_1ghz, 239 .core = core_dpll_params_2128mhz_dra7xx, 240 .per = per_dpll_params_768mhz_dra7xx, 241 .abe = abe_dpll_params_sysclk2_361267khz, 242 .iva = iva_dpll_params_2330mhz_dra7xx, 243 .usb = usb_dpll_params_1920mhz, 244 .ddr = ddr_dpll_params_2128mhz, 245 .gmac = gmac_dpll_params_2000mhz, 246 }; 247 248 struct dplls dra72x_dplls = { 249 .mpu = mpu_dpll_params_1ghz, 250 .core = core_dpll_params_2128mhz_dra7xx, 251 .per = per_dpll_params_768mhz_dra7xx, 252 .abe = abe_dpll_params_sysclk2_361267khz, 253 .iva = iva_dpll_params_2330mhz_dra7xx, 254 .usb = usb_dpll_params_1920mhz, 255 .ddr = ddr_dpll_params_2664mhz, 256 .gmac = gmac_dpll_params_2000mhz, 257 }; 258 259 struct pmic_data palmas = { 260 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 261 .step = 10000, /* 10 mV represented in uV */ 262 /* 263 * Offset codes 1-6 all give the base voltage in Palmas 264 * Offset code 0 switches OFF the SMPS 265 */ 266 .start_code = 6, 267 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, 268 .pmic_bus_init = sri2c_init, 269 .pmic_write = omap_vc_bypass_send_value, 270 .gpio_en = 0, 271 }; 272 273 /* The TPS659038 and TPS65917 are software-compatible, use common struct */ 274 struct pmic_data tps659038 = { 275 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 276 .step = 10000, /* 10 mV represented in uV */ 277 /* 278 * Offset codes 1-6 all give the base voltage in Palmas 279 * Offset code 0 switches OFF the SMPS 280 */ 281 .start_code = 6, 282 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, 283 .pmic_bus_init = gpi2c_init, 284 .pmic_write = palmas_i2c_write_u8, 285 .gpio_en = 0, 286 }; 287 288 /* The LP8732 and LP8733 are software-compatible, use common struct */ 289 struct pmic_data lp8733 = { 290 .base_offset = LP873X_BUCK_BASE_VOLT_UV, 291 .step = 5000, /* 5 mV represented in uV */ 292 /* 293 * Offset codes 0 - 0x13 Invalid. 294 * Offset codes 0x14 0x17 give 10mV steps 295 * Offset codes 0x17 through 0x9D give 5mV steps 296 * So let us start with our operating range from .73V 297 */ 298 .start_code = 0x17, 299 .i2c_slave_addr = 0x60, 300 .pmic_bus_init = gpi2c_init, 301 .pmic_write = palmas_i2c_write_u8, 302 }; 303 304 struct vcores_data omap5430_volts = { 305 .mpu.value[OPP_NOM] = VDD_MPU, 306 .mpu.addr = SMPS_REG_ADDR_12_MPU, 307 .mpu.pmic = &palmas, 308 309 .core.value[OPP_NOM] = VDD_CORE, 310 .core.addr = SMPS_REG_ADDR_8_CORE, 311 .core.pmic = &palmas, 312 313 .mm.value[OPP_NOM] = VDD_MM, 314 .mm.addr = SMPS_REG_ADDR_45_IVA, 315 .mm.pmic = &palmas, 316 }; 317 318 struct vcores_data omap5430_volts_es2 = { 319 .mpu.value[OPP_NOM] = VDD_MPU_ES2, 320 .mpu.addr = SMPS_REG_ADDR_12_MPU, 321 .mpu.pmic = &palmas, 322 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 323 324 .core.value[OPP_NOM] = VDD_CORE_ES2, 325 .core.addr = SMPS_REG_ADDR_8_CORE, 326 .core.pmic = &palmas, 327 328 .mm.value[OPP_NOM] = VDD_MM_ES2, 329 .mm.addr = SMPS_REG_ADDR_45_IVA, 330 .mm.pmic = &palmas, 331 .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, 332 333 .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN, 334 .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, 335 336 .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN, 337 .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, 338 339 .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN, 340 .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, 341 }; 342 343 /* 344 * Enable essential clock domains, modules and 345 * do some additional special settings needed 346 */ 347 void enable_basic_clocks(void) 348 { 349 u32 const clk_domains_essential[] = { 350 (*prcm)->cm_l4per_clkstctrl, 351 (*prcm)->cm_l3init_clkstctrl, 352 (*prcm)->cm_memif_clkstctrl, 353 (*prcm)->cm_l4cfg_clkstctrl, 354 #ifdef CONFIG_DRIVER_TI_CPSW 355 (*prcm)->cm_gmac_clkstctrl, 356 #endif 357 0 358 }; 359 360 u32 const clk_modules_hw_auto_essential[] = { 361 (*prcm)->cm_l3_gpmc_clkctrl, 362 (*prcm)->cm_memif_emif_1_clkctrl, 363 (*prcm)->cm_memif_emif_2_clkctrl, 364 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, 365 (*prcm)->cm_wkup_gpio1_clkctrl, 366 (*prcm)->cm_l4per_gpio2_clkctrl, 367 (*prcm)->cm_l4per_gpio3_clkctrl, 368 (*prcm)->cm_l4per_gpio4_clkctrl, 369 (*prcm)->cm_l4per_gpio5_clkctrl, 370 (*prcm)->cm_l4per_gpio6_clkctrl, 371 (*prcm)->cm_l4per_gpio7_clkctrl, 372 (*prcm)->cm_l4per_gpio8_clkctrl, 373 #ifdef CONFIG_SCSI_AHCI_PLAT 374 (*prcm)->cm_l3init_ocp2scp3_clkctrl, 375 #endif 376 0 377 }; 378 379 u32 const clk_modules_explicit_en_essential[] = { 380 (*prcm)->cm_wkup_gptimer1_clkctrl, 381 (*prcm)->cm_l3init_hsmmc1_clkctrl, 382 (*prcm)->cm_l3init_hsmmc2_clkctrl, 383 (*prcm)->cm_l4per_gptimer2_clkctrl, 384 (*prcm)->cm_wkup_wdtimer2_clkctrl, 385 (*prcm)->cm_l4per_uart3_clkctrl, 386 (*prcm)->cm_l4per_i2c1_clkctrl, 387 #ifdef CONFIG_DRIVER_TI_CPSW 388 (*prcm)->cm_gmac_gmac_clkctrl, 389 #endif 390 391 #ifdef CONFIG_TI_QSPI 392 (*prcm)->cm_l4per_qspi_clkctrl, 393 #endif 394 #ifdef CONFIG_SCSI_AHCI_PLAT 395 (*prcm)->cm_l3init_sata_clkctrl, 396 #endif 397 0 398 }; 399 400 /* Enable optional additional functional clock for GPIO4 */ 401 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, 402 GPIO4_CLKCTRL_OPTFCLKEN_MASK); 403 404 /* Enable 96 MHz clock for MMC1 & MMC2 */ 405 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 406 HSMMC_CLKCTRL_CLKSEL_MASK); 407 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 408 HSMMC_CLKCTRL_CLKSEL_MASK); 409 410 /* Set the correct clock dividers for mmc */ 411 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 412 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 413 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 414 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 415 416 /* Select 32KHz clock as the source of GPTIMER1 */ 417 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, 418 GPTIMER1_CLKCTRL_CLKSEL_MASK); 419 420 do_enable_clocks(clk_domains_essential, 421 clk_modules_hw_auto_essential, 422 clk_modules_explicit_en_essential, 423 1); 424 425 #ifdef CONFIG_TI_QSPI 426 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); 427 #endif 428 429 #ifdef CONFIG_SCSI_AHCI_PLAT 430 /* Enable optional functional clock for SATA */ 431 setbits_le32((*prcm)->cm_l3init_sata_clkctrl, 432 SATA_CLKCTRL_OPTFCLKEN_MASK); 433 #endif 434 435 /* Enable SCRM OPT clocks for PER and CORE dpll */ 436 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 437 OPTFCLKEN_SCRM_PER_MASK); 438 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 439 OPTFCLKEN_SCRM_CORE_MASK); 440 } 441 442 void enable_basic_uboot_clocks(void) 443 { 444 u32 const clk_domains_essential[] = { 445 #if defined(CONFIG_DRA7XX) 446 (*prcm)->cm_ipu_clkstctrl, 447 #endif 448 0 449 }; 450 451 u32 const clk_modules_hw_auto_essential[] = { 452 (*prcm)->cm_l3init_hsusbtll_clkctrl, 453 0 454 }; 455 456 u32 const clk_modules_explicit_en_essential[] = { 457 (*prcm)->cm_l4per_mcspi1_clkctrl, 458 (*prcm)->cm_l4per_i2c2_clkctrl, 459 (*prcm)->cm_l4per_i2c3_clkctrl, 460 (*prcm)->cm_l4per_i2c4_clkctrl, 461 #if defined(CONFIG_DRA7XX) 462 (*prcm)->cm_ipu_i2c5_clkctrl, 463 #else 464 (*prcm)->cm_l4per_i2c5_clkctrl, 465 #endif 466 (*prcm)->cm_l3init_hsusbhost_clkctrl, 467 (*prcm)->cm_l3init_fsusb_clkctrl, 468 0 469 }; 470 do_enable_clocks(clk_domains_essential, 471 clk_modules_hw_auto_essential, 472 clk_modules_explicit_en_essential, 473 1); 474 } 475 476 #ifdef CONFIG_TI_EDMA3 477 void enable_edma3_clocks(void) 478 { 479 u32 const clk_domains_edma3[] = { 480 0 481 }; 482 483 u32 const clk_modules_hw_auto_edma3[] = { 484 (*prcm)->cm_l3main1_tptc1_clkctrl, 485 (*prcm)->cm_l3main1_tptc2_clkctrl, 486 0 487 }; 488 489 u32 const clk_modules_explicit_en_edma3[] = { 490 0 491 }; 492 493 do_enable_clocks(clk_domains_edma3, 494 clk_modules_hw_auto_edma3, 495 clk_modules_explicit_en_edma3, 496 1); 497 } 498 499 void disable_edma3_clocks(void) 500 { 501 u32 const clk_domains_edma3[] = { 502 0 503 }; 504 505 u32 const clk_modules_disable_edma3[] = { 506 (*prcm)->cm_l3main1_tptc1_clkctrl, 507 (*prcm)->cm_l3main1_tptc2_clkctrl, 508 0 509 }; 510 511 do_disable_clocks(clk_domains_edma3, 512 clk_modules_disable_edma3, 513 1); 514 } 515 #endif 516 517 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 518 void enable_usb_clocks(int index) 519 { 520 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 521 522 if (index == 0) { 523 cm_l3init_usb_otg_ss_clkctrl = 524 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 525 /* Enable 960 MHz clock for dwc3 */ 526 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 527 OPTFCLKEN_REFCLK960M); 528 529 /* Enable 32 KHz clock for USB_PHY1 */ 530 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 531 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 532 533 /* Enable 32 KHz clock for USB_PHY3 */ 534 if (is_dra7xx()) 535 setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 536 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 537 } else if (index == 1) { 538 cm_l3init_usb_otg_ss_clkctrl = 539 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 540 /* Enable 960 MHz clock for dwc3 */ 541 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 542 OPTFCLKEN_REFCLK960M); 543 544 /* Enable 32 KHz clock for dwc3 */ 545 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 546 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 547 548 /* Enable 60 MHz clock for USB2PHY2 */ 549 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 550 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 551 } 552 553 u32 const clk_domains_usb[] = { 554 0 555 }; 556 557 u32 const clk_modules_hw_auto_usb[] = { 558 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 559 cm_l3init_usb_otg_ss_clkctrl, 560 0 561 }; 562 563 u32 const clk_modules_explicit_en_usb[] = { 564 0 565 }; 566 567 do_enable_clocks(clk_domains_usb, 568 clk_modules_hw_auto_usb, 569 clk_modules_explicit_en_usb, 570 1); 571 } 572 573 void disable_usb_clocks(int index) 574 { 575 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 576 577 if (index == 0) { 578 cm_l3init_usb_otg_ss_clkctrl = 579 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 580 /* Disable 960 MHz clock for dwc3 */ 581 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 582 OPTFCLKEN_REFCLK960M); 583 584 /* Disable 32 KHz clock for USB_PHY1 */ 585 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 586 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 587 588 /* Disable 32 KHz clock for USB_PHY3 */ 589 if (is_dra7xx()) 590 clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 591 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 592 } else if (index == 1) { 593 cm_l3init_usb_otg_ss_clkctrl = 594 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 595 /* Disable 960 MHz clock for dwc3 */ 596 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 597 OPTFCLKEN_REFCLK960M); 598 599 /* Disable 32 KHz clock for dwc3 */ 600 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 601 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 602 603 /* Disable 60 MHz clock for USB2PHY2 */ 604 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 605 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 606 } 607 608 u32 const clk_domains_usb[] = { 609 0 610 }; 611 612 u32 const clk_modules_disable[] = { 613 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 614 cm_l3init_usb_otg_ss_clkctrl, 615 0 616 }; 617 618 do_disable_clocks(clk_domains_usb, 619 clk_modules_disable, 620 1); 621 } 622 #endif 623 624 const struct ctrl_ioregs ioregs_omap5430 = { 625 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, 626 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, 627 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, 628 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, 629 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, 630 }; 631 632 const struct ctrl_ioregs ioregs_omap5432_es1 = { 633 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, 634 .ctrl_lpddr2ch = 0x0, 635 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, 636 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, 637 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, 638 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, 639 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 640 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 641 }; 642 643 const struct ctrl_ioregs ioregs_omap5432_es2 = { 644 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 645 .ctrl_lpddr2ch = 0x0, 646 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 647 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, 648 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, 649 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, 650 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 651 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 652 }; 653 654 const struct ctrl_ioregs ioregs_dra7xx_es1 = { 655 .ctrl_ddrch = 0x40404040, 656 .ctrl_lpddr2ch = 0x40404040, 657 .ctrl_ddr3ch = 0x80808080, 658 .ctrl_ddrio_0 = 0x00094A40, 659 .ctrl_ddrio_1 = 0x04A52000, 660 .ctrl_ddrio_2 = 0x84210000, 661 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 662 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 663 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 664 }; 665 666 const struct ctrl_ioregs ioregs_dra72x_es1 = { 667 .ctrl_ddrch = 0x40404040, 668 .ctrl_lpddr2ch = 0x40404040, 669 .ctrl_ddr3ch = 0x60606080, 670 .ctrl_ddrio_0 = 0x00094A40, 671 .ctrl_ddrio_1 = 0x04A52000, 672 .ctrl_ddrio_2 = 0x84210000, 673 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 674 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 675 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 676 }; 677 678 const struct ctrl_ioregs ioregs_dra72x_es2 = { 679 .ctrl_ddrch = 0x40404040, 680 .ctrl_lpddr2ch = 0x40404040, 681 .ctrl_ddr3ch = 0x60606060, 682 .ctrl_ddrio_0 = 0x00094A40, 683 .ctrl_ddrio_1 = 0x00000000, 684 .ctrl_ddrio_2 = 0x00000000, 685 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 686 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 687 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 688 }; 689 690 void __weak hw_data_init(void) 691 { 692 u32 omap_rev = omap_revision(); 693 694 switch (omap_rev) { 695 696 case OMAP5430_ES1_0: 697 case OMAP5432_ES1_0: 698 *prcm = &omap5_es1_prcm; 699 *dplls_data = &omap5_dplls_es1; 700 *omap_vcores = &omap5430_volts; 701 *ctrl = &omap5_ctrl; 702 break; 703 704 case OMAP5430_ES2_0: 705 case OMAP5432_ES2_0: 706 *prcm = &omap5_es2_prcm; 707 *dplls_data = &omap5_dplls_es2; 708 *omap_vcores = &omap5430_volts_es2; 709 *ctrl = &omap5_ctrl; 710 break; 711 712 case DRA752_ES1_0: 713 case DRA752_ES1_1: 714 case DRA752_ES2_0: 715 *prcm = &dra7xx_prcm; 716 *dplls_data = &dra7xx_dplls; 717 *ctrl = &dra7xx_ctrl; 718 break; 719 720 case DRA722_ES1_0: 721 case DRA722_ES2_0: 722 *prcm = &dra7xx_prcm; 723 *dplls_data = &dra72x_dplls; 724 *ctrl = &dra7xx_ctrl; 725 break; 726 727 default: 728 printf("\n INVALID OMAP REVISION "); 729 } 730 } 731 732 void get_ioregs(const struct ctrl_ioregs **regs) 733 { 734 u32 omap_rev = omap_revision(); 735 736 switch (omap_rev) { 737 case OMAP5430_ES1_0: 738 case OMAP5430_ES2_0: 739 *regs = &ioregs_omap5430; 740 break; 741 case OMAP5432_ES1_0: 742 *regs = &ioregs_omap5432_es1; 743 break; 744 case OMAP5432_ES2_0: 745 *regs = &ioregs_omap5432_es2; 746 break; 747 case DRA752_ES1_0: 748 case DRA752_ES1_1: 749 case DRA752_ES2_0: 750 *regs = &ioregs_dra7xx_es1; 751 break; 752 case DRA722_ES1_0: 753 *regs = &ioregs_dra72x_es1; 754 break; 755 case DRA722_ES2_0: 756 *regs = &ioregs_dra72x_es2; 757 break; 758 759 default: 760 printf("\n INVALID OMAP REVISION "); 761 } 762 } 763