1 /* 2 * 3 * HW data initialization for OMAP5 4 * 5 * (C) Copyright 2013 6 * Texas Instruments, <www.ti.com> 7 * 8 * Sricharan R <r.sricharan@ti.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #include <common.h> 13 #include <palmas.h> 14 #include <asm/arch/omap.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/omap_common.h> 17 #include <asm/arch/clock.h> 18 #include <asm/omap_gpio.h> 19 #include <asm/io.h> 20 #include <asm/emif.h> 21 22 struct prcm_regs const **prcm = 23 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; 24 struct dplls const **dplls_data = 25 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; 26 struct vcores_data const **omap_vcores = 27 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; 28 struct omap_sys_ctrl_regs const **ctrl = 29 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; 30 31 /* OPP HIGH FREQUENCY for ES2.0 */ 32 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { 33 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 34 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 35 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 36 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 37 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 38 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 39 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 40 }; 41 42 /* OPP NOM FREQUENCY for ES1.0 */ 43 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { 44 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 45 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 46 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 47 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 48 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 49 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 50 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 51 }; 52 53 /* OPP LOW FREQUENCY for ES1.0 */ 54 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { 55 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 56 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 57 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 58 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 59 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 60 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 61 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 62 }; 63 64 /* OPP LOW FREQUENCY for ES2.0 */ 65 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = { 66 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 67 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 68 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 69 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 70 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 71 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 72 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 73 }; 74 75 /* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */ 76 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = { 77 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 78 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 79 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 80 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 81 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 82 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 83 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 84 }; 85 86 static const struct dpll_params 87 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { 88 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ 89 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 90 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ 91 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ 92 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ 93 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 94 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ 95 }; 96 97 static const struct dpll_params 98 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { 99 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */ 100 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 101 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */ 102 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */ 103 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */ 104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 105 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */ 106 }; 107 108 static const struct dpll_params 109 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = { 110 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */ 111 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */ 112 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */ 113 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */ 114 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */ 115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 116 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */ 117 }; 118 119 static const struct dpll_params 120 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { 121 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ 122 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 123 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ 124 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ 125 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ 126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 127 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ 128 }; 129 130 static const struct dpll_params 131 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { 132 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ 133 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 134 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ 135 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ 136 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ 137 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 138 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ 139 }; 140 141 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { 142 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 143 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 144 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 145 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 146 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 147 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 148 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 149 }; 150 151 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { 152 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ 153 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 154 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 155 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 156 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ 157 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 158 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ 159 }; 160 161 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { 162 {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ 163 {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ 164 {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ 165 {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ 166 {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ 167 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 168 {10, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 38.4 MHz */ 169 }; 170 171 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { 172 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 174 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 175 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 176 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 177 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 178 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 179 }; 180 181 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = { 182 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 183 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 184 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 185 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 186 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 188 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 189 }; 190 191 /* ABE M & N values with sys_clk as source */ 192 static const struct dpll_params 193 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { 194 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 195 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 196 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 197 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 198 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 200 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 201 }; 202 203 /* ABE M & N values with 32K clock as source */ 204 static const struct dpll_params abe_dpll_params_32k_196608khz = { 205 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 206 }; 207 208 /* ABE M & N values with sysclk2(22.5792 MHz) as input */ 209 static const struct dpll_params 210 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = { 211 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 212 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 214 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 215 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 216 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 217 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 218 }; 219 220 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { 221 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 222 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 223 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 224 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 225 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 226 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 227 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 228 }; 229 230 static const struct dpll_params ddr_dpll_params_2664mhz[NUM_SYS_CLKS] = { 231 {111, 0, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 232 {333, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 233 {555, 6, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 234 {555, 7, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 235 {666, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 236 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 237 {555, 15, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 238 }; 239 240 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = { 241 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 242 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */ 243 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 244 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 245 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 246 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 247 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 248 }; 249 250 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = { 251 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */ 252 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */ 253 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 254 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 255 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */ 256 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 257 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */ 258 }; 259 260 struct dplls omap5_dplls_es1 = { 261 .mpu = mpu_dpll_params_800mhz, 262 .core = core_dpll_params_2128mhz_ddr532, 263 .per = per_dpll_params_768mhz, 264 .iva = iva_dpll_params_2330mhz, 265 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 266 .abe = abe_dpll_params_sysclk_196608khz, 267 #else 268 .abe = &abe_dpll_params_32k_196608khz, 269 #endif 270 .usb = usb_dpll_params_1920mhz, 271 .ddr = NULL 272 }; 273 274 struct dplls omap5_dplls_es2 = { 275 .mpu = mpu_dpll_params_1ghz, 276 .core = core_dpll_params_2128mhz_ddr532_es2, 277 .per = per_dpll_params_768mhz_es2, 278 .iva = iva_dpll_params_2330mhz, 279 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 280 .abe = abe_dpll_params_sysclk_196608khz, 281 #else 282 .abe = &abe_dpll_params_32k_196608khz, 283 #endif 284 .usb = usb_dpll_params_1920mhz, 285 .ddr = NULL 286 }; 287 288 struct dplls dra7xx_dplls = { 289 .mpu = mpu_dpll_params_1ghz, 290 .core = core_dpll_params_2128mhz_dra7xx, 291 .per = per_dpll_params_768mhz_dra7xx, 292 .abe = abe_dpll_params_sysclk2_361267khz, 293 .iva = iva_dpll_params_2330mhz_dra7xx, 294 .usb = usb_dpll_params_1920mhz, 295 .ddr = ddr_dpll_params_2128mhz, 296 .gmac = gmac_dpll_params_2000mhz, 297 }; 298 299 struct dplls dra72x_dplls = { 300 .mpu = mpu_dpll_params_1ghz, 301 .core = core_dpll_params_2128mhz_dra7xx, 302 .per = per_dpll_params_768mhz_dra7xx, 303 .abe = abe_dpll_params_sysclk2_361267khz, 304 .iva = iva_dpll_params_2330mhz_dra7xx, 305 .usb = usb_dpll_params_1920mhz, 306 .ddr = ddr_dpll_params_2664mhz, 307 .gmac = gmac_dpll_params_2000mhz, 308 }; 309 310 struct pmic_data palmas = { 311 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 312 .step = 10000, /* 10 mV represented in uV */ 313 /* 314 * Offset codes 1-6 all give the base voltage in Palmas 315 * Offset code 0 switches OFF the SMPS 316 */ 317 .start_code = 6, 318 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, 319 .pmic_bus_init = sri2c_init, 320 .pmic_write = omap_vc_bypass_send_value, 321 .gpio_en = 0, 322 }; 323 324 /* The TPS659038 and TPS65917 are software-compatible, use common struct */ 325 struct pmic_data tps659038 = { 326 .base_offset = PALMAS_SMPS_BASE_VOLT_UV, 327 .step = 10000, /* 10 mV represented in uV */ 328 /* 329 * Offset codes 1-6 all give the base voltage in Palmas 330 * Offset code 0 switches OFF the SMPS 331 */ 332 .start_code = 6, 333 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, 334 .pmic_bus_init = gpi2c_init, 335 .pmic_write = palmas_i2c_write_u8, 336 .gpio_en = 0, 337 }; 338 339 /* The LP8732 and LP8733 are software-compatible, use common struct */ 340 struct pmic_data lp8733 = { 341 .base_offset = LP873X_BUCK_BASE_VOLT_UV, 342 .step = 5000, /* 5 mV represented in uV */ 343 /* 344 * Offset codes 0 - 0x13 Invalid. 345 * Offset codes 0x14 0x17 give 10mV steps 346 * Offset codes 0x17 through 0x9D give 5mV steps 347 * So let us start with our operating range from .73V 348 */ 349 .start_code = 0x17, 350 .i2c_slave_addr = 0x60, 351 .pmic_bus_init = gpi2c_init, 352 .pmic_write = palmas_i2c_write_u8, 353 }; 354 355 struct vcores_data omap5430_volts = { 356 .mpu.value[OPP_NOM] = VDD_MPU, 357 .mpu.addr = SMPS_REG_ADDR_12_MPU, 358 .mpu.pmic = &palmas, 359 360 .core.value[OPP_NOM] = VDD_CORE, 361 .core.addr = SMPS_REG_ADDR_8_CORE, 362 .core.pmic = &palmas, 363 364 .mm.value[OPP_NOM] = VDD_MM, 365 .mm.addr = SMPS_REG_ADDR_45_IVA, 366 .mm.pmic = &palmas, 367 }; 368 369 struct vcores_data omap5430_volts_es2 = { 370 .mpu.value[OPP_NOM] = VDD_MPU_ES2, 371 .mpu.addr = SMPS_REG_ADDR_12_MPU, 372 .mpu.pmic = &palmas, 373 .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK, 374 375 .core.value[OPP_NOM] = VDD_CORE_ES2, 376 .core.addr = SMPS_REG_ADDR_8_CORE, 377 .core.pmic = &palmas, 378 379 .mm.value[OPP_NOM] = VDD_MM_ES2, 380 .mm.addr = SMPS_REG_ADDR_45_IVA, 381 .mm.pmic = &palmas, 382 .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, 383 }; 384 385 /* 386 * Enable essential clock domains, modules and 387 * do some additional special settings needed 388 */ 389 void enable_basic_clocks(void) 390 { 391 u32 const clk_domains_essential[] = { 392 (*prcm)->cm_l4per_clkstctrl, 393 (*prcm)->cm_l3init_clkstctrl, 394 (*prcm)->cm_memif_clkstctrl, 395 (*prcm)->cm_l4cfg_clkstctrl, 396 #ifdef CONFIG_DRIVER_TI_CPSW 397 (*prcm)->cm_gmac_clkstctrl, 398 #endif 399 0 400 }; 401 402 u32 const clk_modules_hw_auto_essential[] = { 403 (*prcm)->cm_l3_gpmc_clkctrl, 404 (*prcm)->cm_memif_emif_1_clkctrl, 405 (*prcm)->cm_memif_emif_2_clkctrl, 406 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, 407 (*prcm)->cm_wkup_gpio1_clkctrl, 408 (*prcm)->cm_l4per_gpio2_clkctrl, 409 (*prcm)->cm_l4per_gpio3_clkctrl, 410 (*prcm)->cm_l4per_gpio4_clkctrl, 411 (*prcm)->cm_l4per_gpio5_clkctrl, 412 (*prcm)->cm_l4per_gpio6_clkctrl, 413 (*prcm)->cm_l4per_gpio7_clkctrl, 414 (*prcm)->cm_l4per_gpio8_clkctrl, 415 0 416 }; 417 418 u32 const clk_modules_explicit_en_essential[] = { 419 (*prcm)->cm_wkup_gptimer1_clkctrl, 420 (*prcm)->cm_l3init_hsmmc1_clkctrl, 421 (*prcm)->cm_l3init_hsmmc2_clkctrl, 422 (*prcm)->cm_l4per_gptimer2_clkctrl, 423 (*prcm)->cm_wkup_wdtimer2_clkctrl, 424 (*prcm)->cm_l4per_uart3_clkctrl, 425 (*prcm)->cm_l4per_i2c1_clkctrl, 426 #ifdef CONFIG_DRIVER_TI_CPSW 427 (*prcm)->cm_gmac_gmac_clkctrl, 428 #endif 429 430 #ifdef CONFIG_TI_QSPI 431 (*prcm)->cm_l4per_qspi_clkctrl, 432 #endif 433 0 434 }; 435 436 /* Enable optional additional functional clock for GPIO4 */ 437 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, 438 GPIO4_CLKCTRL_OPTFCLKEN_MASK); 439 440 /* Enable 96 MHz clock for MMC1 & MMC2 */ 441 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 442 HSMMC_CLKCTRL_CLKSEL_MASK); 443 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 444 HSMMC_CLKCTRL_CLKSEL_MASK); 445 446 /* Set the correct clock dividers for mmc */ 447 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 448 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 449 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 450 HSMMC_CLKCTRL_CLKSEL_DIV_MASK); 451 452 /* Select 32KHz clock as the source of GPTIMER1 */ 453 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, 454 GPTIMER1_CLKCTRL_CLKSEL_MASK); 455 456 do_enable_clocks(clk_domains_essential, 457 clk_modules_hw_auto_essential, 458 clk_modules_explicit_en_essential, 459 1); 460 461 #ifdef CONFIG_TI_QSPI 462 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); 463 #endif 464 465 /* Enable SCRM OPT clocks for PER and CORE dpll */ 466 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 467 OPTFCLKEN_SCRM_PER_MASK); 468 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, 469 OPTFCLKEN_SCRM_CORE_MASK); 470 } 471 472 void enable_basic_uboot_clocks(void) 473 { 474 u32 const clk_domains_essential[] = { 475 #if defined(CONFIG_DRA7XX) 476 (*prcm)->cm_ipu_clkstctrl, 477 #endif 478 0 479 }; 480 481 u32 const clk_modules_hw_auto_essential[] = { 482 (*prcm)->cm_l3init_hsusbtll_clkctrl, 483 0 484 }; 485 486 u32 const clk_modules_explicit_en_essential[] = { 487 (*prcm)->cm_l4per_mcspi1_clkctrl, 488 (*prcm)->cm_l4per_i2c2_clkctrl, 489 (*prcm)->cm_l4per_i2c3_clkctrl, 490 (*prcm)->cm_l4per_i2c4_clkctrl, 491 #if defined(CONFIG_DRA7XX) 492 (*prcm)->cm_ipu_i2c5_clkctrl, 493 #else 494 (*prcm)->cm_l4per_i2c5_clkctrl, 495 #endif 496 (*prcm)->cm_l3init_hsusbhost_clkctrl, 497 (*prcm)->cm_l3init_fsusb_clkctrl, 498 0 499 }; 500 do_enable_clocks(clk_domains_essential, 501 clk_modules_hw_auto_essential, 502 clk_modules_explicit_en_essential, 503 1); 504 } 505 506 #ifdef CONFIG_TI_EDMA3 507 void enable_edma3_clocks(void) 508 { 509 u32 const clk_domains_edma3[] = { 510 0 511 }; 512 513 u32 const clk_modules_hw_auto_edma3[] = { 514 (*prcm)->cm_l3main1_tptc1_clkctrl, 515 (*prcm)->cm_l3main1_tptc2_clkctrl, 516 0 517 }; 518 519 u32 const clk_modules_explicit_en_edma3[] = { 520 0 521 }; 522 523 do_enable_clocks(clk_domains_edma3, 524 clk_modules_hw_auto_edma3, 525 clk_modules_explicit_en_edma3, 526 1); 527 } 528 529 void disable_edma3_clocks(void) 530 { 531 u32 const clk_domains_edma3[] = { 532 0 533 }; 534 535 u32 const clk_modules_disable_edma3[] = { 536 (*prcm)->cm_l3main1_tptc1_clkctrl, 537 (*prcm)->cm_l3main1_tptc2_clkctrl, 538 0 539 }; 540 541 do_disable_clocks(clk_domains_edma3, 542 clk_modules_disable_edma3, 543 1); 544 } 545 #endif 546 547 #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP) 548 void enable_usb_clocks(int index) 549 { 550 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 551 552 if (index == 0) { 553 cm_l3init_usb_otg_ss_clkctrl = 554 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 555 /* Enable 960 MHz clock for dwc3 */ 556 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 557 OPTFCLKEN_REFCLK960M); 558 559 /* Enable 32 KHz clock for USB_PHY1 */ 560 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 561 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 562 563 /* Enable 32 KHz clock for USB_PHY3 */ 564 if (is_dra7xx()) 565 setbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 566 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 567 } else if (index == 1) { 568 cm_l3init_usb_otg_ss_clkctrl = 569 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 570 /* Enable 960 MHz clock for dwc3 */ 571 setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 572 OPTFCLKEN_REFCLK960M); 573 574 /* Enable 32 KHz clock for dwc3 */ 575 setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 576 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 577 578 /* Enable 60 MHz clock for USB2PHY2 */ 579 setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 580 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 581 } 582 583 u32 const clk_domains_usb[] = { 584 0 585 }; 586 587 u32 const clk_modules_hw_auto_usb[] = { 588 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 589 cm_l3init_usb_otg_ss_clkctrl, 590 0 591 }; 592 593 u32 const clk_modules_explicit_en_usb[] = { 594 0 595 }; 596 597 do_enable_clocks(clk_domains_usb, 598 clk_modules_hw_auto_usb, 599 clk_modules_explicit_en_usb, 600 1); 601 } 602 603 void disable_usb_clocks(int index) 604 { 605 u32 cm_l3init_usb_otg_ss_clkctrl = 0; 606 607 if (index == 0) { 608 cm_l3init_usb_otg_ss_clkctrl = 609 (*prcm)->cm_l3init_usb_otg_ss1_clkctrl; 610 /* Disable 960 MHz clock for dwc3 */ 611 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, 612 OPTFCLKEN_REFCLK960M); 613 614 /* Disable 32 KHz clock for USB_PHY1 */ 615 clrbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 616 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 617 618 /* Disable 32 KHz clock for USB_PHY3 */ 619 if (is_dra7xx()) 620 clrbits_le32((*prcm)->cm_coreaon_usb_phy3_core_clkctrl, 621 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 622 } else if (index == 1) { 623 cm_l3init_usb_otg_ss_clkctrl = 624 (*prcm)->cm_l3init_usb_otg_ss2_clkctrl; 625 /* Disable 960 MHz clock for dwc3 */ 626 clrbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl, 627 OPTFCLKEN_REFCLK960M); 628 629 /* Disable 32 KHz clock for dwc3 */ 630 clrbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl, 631 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 632 633 /* Disable 60 MHz clock for USB2PHY2 */ 634 clrbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl, 635 L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK); 636 } 637 638 u32 const clk_domains_usb[] = { 639 0 640 }; 641 642 u32 const clk_modules_disable[] = { 643 (*prcm)->cm_l3init_ocp2scp1_clkctrl, 644 cm_l3init_usb_otg_ss_clkctrl, 645 0 646 }; 647 648 do_disable_clocks(clk_domains_usb, 649 clk_modules_disable, 650 1); 651 } 652 #endif 653 654 const struct ctrl_ioregs ioregs_omap5430 = { 655 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, 656 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, 657 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, 658 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, 659 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, 660 }; 661 662 const struct ctrl_ioregs ioregs_omap5432_es1 = { 663 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, 664 .ctrl_lpddr2ch = 0x0, 665 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, 666 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE, 667 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE, 668 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE, 669 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 670 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 671 }; 672 673 const struct ctrl_ioregs ioregs_omap5432_es2 = { 674 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 675 .ctrl_lpddr2ch = 0x0, 676 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, 677 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, 678 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, 679 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, 680 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, 681 .ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, 682 }; 683 684 const struct ctrl_ioregs ioregs_dra7xx_es1 = { 685 .ctrl_ddrch = 0x40404040, 686 .ctrl_lpddr2ch = 0x40404040, 687 .ctrl_ddr3ch = 0x80808080, 688 .ctrl_ddrio_0 = 0x00094A40, 689 .ctrl_ddrio_1 = 0x04A52000, 690 .ctrl_ddrio_2 = 0x84210000, 691 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 692 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 693 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 694 }; 695 696 const struct ctrl_ioregs ioregs_dra72x_es1 = { 697 .ctrl_ddrch = 0x40404040, 698 .ctrl_lpddr2ch = 0x40404040, 699 .ctrl_ddr3ch = 0x60606080, 700 .ctrl_ddrio_0 = 0x00094A40, 701 .ctrl_ddrio_1 = 0x04A52000, 702 .ctrl_ddrio_2 = 0x84210000, 703 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 704 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 705 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 706 }; 707 708 const struct ctrl_ioregs ioregs_dra72x_es2 = { 709 .ctrl_ddrch = 0x40404040, 710 .ctrl_lpddr2ch = 0x40404040, 711 .ctrl_ddr3ch = 0x60606060, 712 .ctrl_ddrio_0 = 0x00094A40, 713 .ctrl_ddrio_1 = 0x00000000, 714 .ctrl_ddrio_2 = 0x00000000, 715 .ctrl_emif_sdram_config_ext = 0x0001C1A7, 716 .ctrl_emif_sdram_config_ext_final = 0x0001C1A7, 717 .ctrl_ddr_ctrl_ext_0 = 0xA2000000, 718 }; 719 720 void __weak hw_data_init(void) 721 { 722 u32 omap_rev = omap_revision(); 723 724 switch (omap_rev) { 725 726 case OMAP5430_ES1_0: 727 case OMAP5432_ES1_0: 728 *prcm = &omap5_es1_prcm; 729 *dplls_data = &omap5_dplls_es1; 730 *omap_vcores = &omap5430_volts; 731 *ctrl = &omap5_ctrl; 732 break; 733 734 case OMAP5430_ES2_0: 735 case OMAP5432_ES2_0: 736 *prcm = &omap5_es2_prcm; 737 *dplls_data = &omap5_dplls_es2; 738 *omap_vcores = &omap5430_volts_es2; 739 *ctrl = &omap5_ctrl; 740 break; 741 742 case DRA752_ES1_0: 743 case DRA752_ES1_1: 744 case DRA752_ES2_0: 745 *prcm = &dra7xx_prcm; 746 *dplls_data = &dra7xx_dplls; 747 *ctrl = &dra7xx_ctrl; 748 break; 749 750 case DRA722_ES1_0: 751 case DRA722_ES2_0: 752 *prcm = &dra7xx_prcm; 753 *dplls_data = &dra72x_dplls; 754 *ctrl = &dra7xx_ctrl; 755 break; 756 757 default: 758 printf("\n INVALID OMAP REVISION "); 759 } 760 } 761 762 void get_ioregs(const struct ctrl_ioregs **regs) 763 { 764 u32 omap_rev = omap_revision(); 765 766 switch (omap_rev) { 767 case OMAP5430_ES1_0: 768 case OMAP5430_ES2_0: 769 *regs = &ioregs_omap5430; 770 break; 771 case OMAP5432_ES1_0: 772 *regs = &ioregs_omap5432_es1; 773 break; 774 case OMAP5432_ES2_0: 775 *regs = &ioregs_omap5432_es2; 776 break; 777 case DRA752_ES1_0: 778 case DRA752_ES1_1: 779 case DRA752_ES2_0: 780 *regs = &ioregs_dra7xx_es1; 781 break; 782 case DRA722_ES1_0: 783 *regs = &ioregs_dra72x_es1; 784 break; 785 case DRA722_ES2_0: 786 *regs = &ioregs_dra72x_es2; 787 break; 788 789 default: 790 printf("\n INVALID OMAP REVISION "); 791 } 792 } 793