xref: /openbmc/u-boot/arch/arm/mach-omap2/omap5/fdt.c (revision e9c847c3) 
1 /*
2  * Copyright 2016 Texas Instruments, Inc.
3  *
4  * SPDX-License-Identifier: GPL-2.0+
5  */
6 
7 #include <common.h>
8 #include <libfdt.h>
9 #include <fdt_support.h>
10 #include <malloc.h>
11 
12 #include <asm/omap_common.h>
13 #include <asm/arch-omap5/sys_proto.h>
14 
15 #ifdef CONFIG_TI_SECURE_DEVICE
16 
17 /* Give zero values if not already defined */
18 #ifndef TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ
19 #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ (0)
20 #endif
21 #ifndef CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
22 #define CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ (0)
23 #endif
24 
25 static u32 hs_irq_skip[] = {
26 	8,	/* Secure violation reporting interrupt */
27 	15,	/* One interrupt for SDMA by secure world */
28 	118	/* One interrupt for Crypto DMA by secure world */
29 };
30 
31 static int ft_hs_fixup_crossbar(void *fdt, bd_t *bd)
32 {
33 	const char *path;
34 	int offs;
35 	int ret;
36 	int len, i, old_cnt, new_cnt;
37 	u32 *temp;
38 	const u32 *p_data;
39 
40 	/*
41 	 * Increase the size of the fdt
42 	 * so we have some breathing room
43 	 */
44 	ret = fdt_increase_size(fdt, 512);
45 	if (ret < 0) {
46 		printf("Could not increase size of device tree: %s\n",
47 		       fdt_strerror(ret));
48 		return ret;
49 	}
50 
51 	/* Reserve IRQs that are used/needed by secure world */
52 	path = "/ocp/crossbar";
53 	offs = fdt_path_offset(fdt, path);
54 	if (offs < 0) {
55 		debug("Node %s not found.\n", path);
56 		return 0;
57 	}
58 
59 	/* Get current entries */
60 	p_data = fdt_getprop(fdt, offs, "ti,irqs-skip", &len);
61 	if (p_data)
62 		old_cnt = len / sizeof(u32);
63 	else
64 		old_cnt = 0;
65 
66 	new_cnt = sizeof(hs_irq_skip) /
67 				sizeof(hs_irq_skip[0]);
68 
69 	/* Create new/updated skip list for HS parts */
70 	temp = malloc(sizeof(u32) * (old_cnt + new_cnt));
71 	for (i = 0; i < new_cnt; i++)
72 		temp[i] = cpu_to_fdt32(hs_irq_skip[i]);
73 	for (i = 0; i < old_cnt; i++)
74 		temp[i + new_cnt] = p_data[i];
75 
76 	/* Blow away old data and set new data */
77 	fdt_delprop(fdt, offs, "ti,irqs-skip");
78 	ret = fdt_setprop(fdt, offs, "ti,irqs-skip",
79 			  temp,
80 			  (old_cnt + new_cnt) * sizeof(u32));
81 	free(temp);
82 
83 	/* Check if the update worked */
84 	if (ret < 0) {
85 		printf("Could not add ti,irqs-skip property to node %s: %s\n",
86 		       path, fdt_strerror(ret));
87 		return ret;
88 	}
89 
90 	return 0;
91 }
92 
93 static int ft_hs_disable_rng(void *fdt, bd_t *bd)
94 {
95 	const char *path;
96 	int offs;
97 	int ret;
98 
99 	/* Make HW RNG reserved for secure world use */
100 	path = "/ocp/rng";
101 	offs = fdt_path_offset(fdt, path);
102 	if (offs < 0) {
103 		debug("Node %s not found.\n", path);
104 		return 0;
105 	}
106 	ret = fdt_setprop_string(fdt, offs,
107 				 "status", "disabled");
108 	if (ret < 0) {
109 		printf("Could not add status property to node %s: %s\n",
110 		       path, fdt_strerror(ret));
111 		return ret;
112 	}
113 	return 0;
114 }
115 
116 #if ((TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ != 0) || \
117     (CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ != 0))
118 static int ft_hs_fixup_sram(void *fdt, bd_t *bd)
119 {
120 	const char *path;
121 	int offs;
122 	int ret;
123 	u32 temp[2];
124 
125 	/*
126 	 * Update SRAM reservations on secure devices. The OCMC RAM
127 	 * is always reserved for secure use from the start of that
128 	 * memory region
129 	 */
130 	path = "/ocp/ocmcram@40300000/sram-hs";
131 	offs = fdt_path_offset(fdt, path);
132 	if (offs < 0) {
133 		debug("Node %s not found.\n", path);
134 		return 0;
135 	}
136 
137 	/* relative start offset */
138 	temp[0] = cpu_to_fdt32(0);
139 	/* reservation size */
140 	temp[1] = cpu_to_fdt32(max(TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ,
141 				   CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ));
142 	fdt_delprop(fdt, offs, "reg");
143 	ret = fdt_setprop(fdt, offs, "reg", temp, 2 * sizeof(u32));
144 	if (ret < 0) {
145 		printf("Could not add reg property to node %s: %s\n",
146 		       path, fdt_strerror(ret));
147 		return ret;
148 	}
149 
150 	return 0;
151 }
152 #else
153 static int ft_hs_fixup_sram(void *fdt, bd_t *bd) { return 0; }
154 #endif
155 
156 #if (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE != 0)
157 static int ft_hs_fixup_dram(void *fdt, bd_t *bd)
158 {
159 	const char *path, *subpath;
160 	int offs;
161 	u32 sec_mem_start = CONFIG_TI_SECURE_EMIF_REGION_START;
162 	u32 sec_mem_size = CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE;
163 	fdt64_t temp[2];
164 
165 	/* If start address is zero, place at end of DRAM */
166 	if (0 == sec_mem_start)
167 		sec_mem_start =
168 			(CONFIG_SYS_SDRAM_BASE +
169 			(omap_sdram_size() - sec_mem_size));
170 
171 	/* Delete any original secure_reserved node */
172 	path = "/reserved-memory/secure_reserved";
173 	offs = fdt_path_offset(fdt, path);
174 	if (offs >= 0)
175 		fdt_del_node(fdt, offs);
176 
177 	/* Add new secure_reserved node */
178 	path = "/reserved-memory";
179 	offs = fdt_path_offset(fdt, path);
180 	if (offs < 0) {
181 		debug("Node %s not found\n", path);
182 		path = "/";
183 		subpath = "reserved-memory";
184 		fdt_path_offset(fdt, path);
185 		offs = fdt_add_subnode(fdt, offs, subpath);
186 		if (offs < 0) {
187 			printf("Could not create %s%s node.\n", path, subpath);
188 			return 1;
189 		}
190 		path = "/reserved-memory";
191 		offs = fdt_path_offset(fdt, path);
192 	}
193 
194 	subpath = "secure_reserved";
195 	offs = fdt_add_subnode(fdt, offs, subpath);
196 	if (offs < 0) {
197 		printf("Could not create %s%s node.\n", path, subpath);
198 		return 1;
199 	}
200 
201 	temp[0] = cpu_to_fdt64(((u64)sec_mem_start));
202 	temp[1] = cpu_to_fdt64(((u64)sec_mem_size));
203 	fdt_setprop_string(fdt, offs, "compatible",
204 			   "ti,dra7-secure-memory");
205 	fdt_setprop_string(fdt, offs, "status", "okay");
206 	fdt_setprop(fdt, offs, "no-map", NULL, 0);
207 	fdt_setprop(fdt, offs, "reg", temp, sizeof(temp));
208 
209 	return 0;
210 }
211 #else
212 static int ft_hs_fixup_dram(void *fdt, bd_t *bd) { return 0; }
213 #endif
214 
215 static int ft_hs_add_tee(void *fdt, bd_t *bd)
216 {
217 	const char *path, *subpath;
218 	int offs;
219 
220 	extern int tee_loaded;
221 	if (!tee_loaded)
222 		return 0;
223 
224 	path = "/";
225 	offs = fdt_path_offset(fdt, path);
226 
227 	subpath = "firmware";
228 	offs = fdt_add_subnode(fdt, offs, subpath);
229 	if (offs < 0) {
230 		printf("Could not create %s node.\n", subpath);
231 		return 1;
232 	}
233 
234 	subpath = "optee";
235 	offs = fdt_add_subnode(fdt, offs, subpath);
236 	if (offs < 0) {
237 		printf("Could not create %s node.\n", subpath);
238 		return 1;
239 	}
240 
241 	fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
242 	fdt_setprop_string(fdt, offs, "method", "smc");
243 
244 	return 0;
245 }
246 
247 static void ft_hs_fixups(void *fdt, bd_t *bd)
248 {
249 	/* Check we are running on an HS/EMU device type */
250 	if (GP_DEVICE != get_device_type()) {
251 		if ((ft_hs_fixup_crossbar(fdt, bd) == 0) &&
252 		    (ft_hs_disable_rng(fdt, bd) == 0) &&
253 		    (ft_hs_fixup_sram(fdt, bd) == 0) &&
254 		    (ft_hs_fixup_dram(fdt, bd) == 0) &&
255 		    (ft_hs_add_tee(fdt, bd) == 0))
256 			return;
257 	} else {
258 		printf("ERROR: Incorrect device type (GP) detected!");
259 	}
260 	/* Fixup failed or wrong device type */
261 	hang();
262 }
263 #else
264 static void ft_hs_fixups(void *fdt, bd_t *bd)
265 {
266 }
267 #endif /* #ifdef CONFIG_TI_SECURE_DEVICE */
268 
269 #if defined(CONFIG_TARGET_DRA7XX_EVM) || defined(CONFIG_TARGET_AM57XX_EVM)
270 #define OPP_DSP_CLK_NUM	3
271 #define OPP_IVA_CLK_NUM	2
272 #define OPP_GPU_CLK_NUM	2
273 
274 const char *dra7_opp_dsp_clk_names[OPP_DSP_CLK_NUM] = {
275 	"dpll_dsp_ck",
276 	"dpll_dsp_m2_ck",
277 	"dpll_dsp_m3x2_ck",
278 };
279 
280 const char *dra7_opp_iva_clk_names[OPP_IVA_CLK_NUM] = {
281 	"dpll_iva_ck",
282 	"dpll_iva_m2_ck",
283 };
284 
285 const char *dra7_opp_gpu_clk_names[OPP_GPU_CLK_NUM] = {
286 	"dpll_gpu_ck",
287 	"dpll_gpu_m2_ck",
288 };
289 
290 /* DSPEVE voltage domain */
291 u32 dra7_opp_dsp_clk_rates[NUM_OPPS][OPP_DSP_CLK_NUM] = {
292 	{}, /*OPP_LOW */
293 	{600000000, 600000000, 400000000}, /* OPP_NOM */
294 	{700000000, 700000000, 466666667}, /* OPP_OD */
295 	{750000000, 750000000, 500000000}, /* OPP_HIGH */
296 };
297 
298 /* IVA voltage domain */
299 u32 dra7_opp_iva_clk_rates[NUM_OPPS][OPP_IVA_CLK_NUM] = {
300 	{}, /* OPP_LOW */
301 	{1165000000, 388333334}, /* OPP_NOM */
302 	{860000000, 430000000}, /* OPP_OD */
303 	{1064000000, 532000000}, /* OPP_HIGH */
304 };
305 
306 /* GPU voltage domain */
307 u32 dra7_opp_gpu_clk_rates[NUM_OPPS][OPP_GPU_CLK_NUM] = {
308 	{}, /* OPP_LOW */
309 	{1277000000, 425666667}, /* OPP_NOM */
310 	{1000000000, 500000000}, /* OPP_OD */
311 	{1064000000, 532000000}, /* OPP_HIGH */
312 };
313 
314 static int ft_fixup_clocks(void *fdt, const char **names, u32 *rates, int num)
315 {
316 	int offs, node_offs, ret, i;
317 	uint32_t phandle;
318 
319 	offs = fdt_path_offset(fdt, "/ocp/l4@4a000000/cm_core_aon@5000/clocks");
320 	if (offs < 0) {
321 		debug("Could not find cm_core_aon clocks node path offset : %s\n",
322 		      fdt_strerror(offs));
323 		return offs;
324 	}
325 
326 	for (i = 0; i < num; i++) {
327 		node_offs = fdt_subnode_offset(fdt, offs, names[i]);
328 		if (node_offs < 0) {
329 			debug("Could not find clock sub-node %s: %s\n",
330 			      names[i], fdt_strerror(node_offs));
331 			return offs;
332 		}
333 
334 		phandle = fdt_get_phandle(fdt, node_offs);
335 		if (!phandle) {
336 			debug("Could not find phandle for clock %s\n",
337 			      names[i]);
338 			return -1;
339 		}
340 
341 		ret = fdt_setprop_u32(fdt, node_offs, "assigned-clocks",
342 				      phandle);
343 		if (ret < 0) {
344 			debug("Could not add assigned-clocks property to clock node %s: %s\n",
345 			      names[i], fdt_strerror(ret));
346 			return ret;
347 		}
348 
349 		ret = fdt_setprop_u32(fdt, node_offs, "assigned-clock-rates",
350 				      rates[i]);
351 		if (ret < 0) {
352 			debug("Could not add assigned-clock-rates property to clock node %s: %s\n",
353 			      names[i], fdt_strerror(ret));
354 			return ret;
355 		}
356 	}
357 
358 	return 0;
359 }
360 
361 static void ft_opp_clock_fixups(void *fdt, bd_t *bd)
362 {
363 	const char **clk_names;
364 	u32 *clk_rates;
365 	int ret;
366 
367 	if (!is_dra72x() && !is_dra7xx())
368 		return;
369 
370 	/* fixup DSP clocks */
371 	clk_names = dra7_opp_dsp_clk_names;
372 	clk_rates = dra7_opp_dsp_clk_rates[get_voltrail_opp(VOLT_EVE)];
373 	ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_DSP_CLK_NUM);
374 	if (ret) {
375 		printf("ft_fixup_clocks failed for DSP voltage domain: %s\n",
376 		       fdt_strerror(ret));
377 		return;
378 	}
379 
380 	/* fixup IVA clocks */
381 	clk_names = dra7_opp_iva_clk_names;
382 	clk_rates = dra7_opp_iva_clk_rates[get_voltrail_opp(VOLT_IVA)];
383 	ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_IVA_CLK_NUM);
384 	if (ret) {
385 		printf("ft_fixup_clocks failed for IVA voltage domain: %s\n",
386 		       fdt_strerror(ret));
387 		return;
388 	}
389 
390 	/* fixup GPU clocks */
391 	clk_names = dra7_opp_gpu_clk_names;
392 	clk_rates = dra7_opp_gpu_clk_rates[get_voltrail_opp(VOLT_GPU)];
393 	ret = ft_fixup_clocks(fdt, clk_names, clk_rates, OPP_GPU_CLK_NUM);
394 	if (ret) {
395 		printf("ft_fixup_clocks failed for GPU voltage domain: %s\n",
396 		       fdt_strerror(ret));
397 		return;
398 	}
399 }
400 #else
401 static void ft_opp_clock_fixups(void *fdt, bd_t *bd) { }
402 #endif /* CONFIG_TARGET_DRA7XX_EVM || CONFIG_TARGET_AM57XX_EVM */
403 
404 /*
405  * Place for general cpu/SoC FDT fixups. Board specific
406  * fixups should remain in the board files which is where
407  * this function should be called from.
408  */
409 void ft_cpu_setup(void *fdt, bd_t *bd)
410 {
411 	ft_hs_fixups(fdt, bd);
412 	ft_opp_clock_fixups(fdt, bd);
413 }
414