1 /* 2 * 3 * Common functions for OMAP4 based boards 4 * 5 * (C) Copyright 2010 6 * Texas Instruments, <www.ti.com> 7 * 8 * Author : 9 * Aneesh V <aneesh@ti.com> 10 * Steve Sakoman <steve@sakoman.com> 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 #include <common.h> 15 #include <asm/armv7.h> 16 #include <asm/arch/cpu.h> 17 #include <asm/arch/sys_proto.h> 18 #include <linux/sizes.h> 19 #include <asm/emif.h> 20 #include <asm/arch/gpio.h> 21 #include <asm/omap_common.h> 22 23 DECLARE_GLOBAL_DATA_PTR; 24 25 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV; 26 27 static const struct gpio_bank gpio_bank_44xx[6] = { 28 { (void *)OMAP44XX_GPIO1_BASE }, 29 { (void *)OMAP44XX_GPIO2_BASE }, 30 { (void *)OMAP44XX_GPIO3_BASE }, 31 { (void *)OMAP44XX_GPIO4_BASE }, 32 { (void *)OMAP44XX_GPIO5_BASE }, 33 { (void *)OMAP44XX_GPIO6_BASE }, 34 }; 35 36 const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx; 37 38 #ifdef CONFIG_SPL_BUILD 39 /* 40 * Some tuning of IOs for optimal power and performance 41 */ 42 void do_io_settings(void) 43 { 44 u32 lpddr2io; 45 46 u32 omap4_rev = omap_revision(); 47 48 if (omap4_rev == OMAP4430_ES1_0) 49 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN; 50 else if (omap4_rev == OMAP4430_ES2_0) 51 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER; 52 else 53 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN; 54 55 /* EMIF1 */ 56 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0); 57 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1); 58 /* No pull for GR10 as per hw team's recommendation */ 59 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, 60 (*ctrl)->control_lpddr2io1_2); 61 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3); 62 63 /* EMIF2 */ 64 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0); 65 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1); 66 /* No pull for GR10 as per hw team's recommendation */ 67 writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK, 68 (*ctrl)->control_lpddr2io2_2); 69 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3); 70 71 /* 72 * Some of these settings (TRIM values) come from eFuse and are 73 * in turn programmed in the eFuse at manufacturing time after 74 * calibration of the device. Do the software over-ride only if 75 * the device is not correctly trimmed 76 */ 77 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) { 78 79 writel(LDOSRAM_VOLT_CTRL_OVERRIDE, 80 (*ctrl)->control_ldosram_iva_voltage_ctrl); 81 82 writel(LDOSRAM_VOLT_CTRL_OVERRIDE, 83 (*ctrl)->control_ldosram_mpu_voltage_ctrl); 84 85 writel(LDOSRAM_VOLT_CTRL_OVERRIDE, 86 (*ctrl)->control_ldosram_core_voltage_ctrl); 87 } 88 89 /* 90 * Over-ride the register 91 * i. unconditionally for all 4430 92 * ii. only if un-trimmed for 4460 93 */ 94 if (!readl((*ctrl)->control_efuse_1)) 95 writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1); 96 97 if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2)) 98 writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2); 99 } 100 #endif /* CONFIG_SPL_BUILD */ 101 102 /* dummy fuction for omap4 */ 103 void config_data_eye_leveling_samples(u32 emif_base) 104 { 105 } 106 107 void init_omap_revision(void) 108 { 109 /* 110 * For some of the ES2/ES1 boards ID_CODE is not reliable: 111 * Also, ES1 and ES2 have different ARM revisions 112 * So use ARM revision for identification 113 */ 114 unsigned int arm_rev = cortex_rev(); 115 116 switch (arm_rev) { 117 case MIDR_CORTEX_A9_R0P1: 118 *omap_si_rev = OMAP4430_ES1_0; 119 break; 120 case MIDR_CORTEX_A9_R1P2: 121 switch (readl(CONTROL_ID_CODE)) { 122 case OMAP4_CONTROL_ID_CODE_ES2_0: 123 *omap_si_rev = OMAP4430_ES2_0; 124 break; 125 case OMAP4_CONTROL_ID_CODE_ES2_1: 126 *omap_si_rev = OMAP4430_ES2_1; 127 break; 128 case OMAP4_CONTROL_ID_CODE_ES2_2: 129 *omap_si_rev = OMAP4430_ES2_2; 130 break; 131 default: 132 *omap_si_rev = OMAP4430_ES2_0; 133 break; 134 } 135 break; 136 case MIDR_CORTEX_A9_R1P3: 137 *omap_si_rev = OMAP4430_ES2_3; 138 break; 139 case MIDR_CORTEX_A9_R2P10: 140 switch (readl(CONTROL_ID_CODE)) { 141 case OMAP4470_CONTROL_ID_CODE_ES1_0: 142 *omap_si_rev = OMAP4470_ES1_0; 143 break; 144 case OMAP4460_CONTROL_ID_CODE_ES1_1: 145 *omap_si_rev = OMAP4460_ES1_1; 146 break; 147 case OMAP4460_CONTROL_ID_CODE_ES1_0: 148 default: 149 *omap_si_rev = OMAP4460_ES1_0; 150 break; 151 } 152 break; 153 default: 154 *omap_si_rev = OMAP4430_SILICON_ID_INVALID; 155 break; 156 } 157 } 158 159 void omap_die_id(unsigned int *die_id) 160 { 161 die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0); 162 die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1); 163 die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2); 164 die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3); 165 } 166 167 #ifndef CONFIG_SYS_L2CACHE_OFF 168 void v7_outer_cache_enable(void) 169 { 170 omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1); 171 } 172 173 void v7_outer_cache_disable(void) 174 { 175 omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0); 176 } 177 #endif /* !CONFIG_SYS_L2CACHE_OFF */ 178