1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *
4  * HW data initialization for OMAP4
5  *
6  * (C) Copyright 2013
7  * Texas Instruments, <www.ti.com>
8  *
9  * Sricharan R <r.sricharan@ti.com>
10  */
11 #include <common.h>
12 #include <asm/arch/omap.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/omap_common.h>
15 #include <asm/arch/clock.h>
16 #include <asm/omap_gpio.h>
17 #include <asm/io.h>
18 
19 struct prcm_regs const **prcm =
20 			(struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
21 struct dplls const **dplls_data =
22 			(struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
23 struct vcores_data const **omap_vcores =
24 		(struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
25 struct omap_sys_ctrl_regs const **ctrl =
26 	(struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
27 
28 /*
29  * The M & N values in the following tables are created using the
30  * following tool:
31  * tools/omap/clocks_get_m_n.c
32  * Please use this tool for creating the table for any new frequency.
33  */
34 
35 /*
36  * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF
37  * OMAP4460 OPP_NOM frequency
38  */
39 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
40 	{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
41 	{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
42 	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
43 	{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
44 	{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
45 	{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
46 	{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
47 };
48 
49 /*
50  * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430)
51  * OMAP4430 OPP_TURBO frequency
52  * OMAP4470 OPP_NOM frequency
53  */
54 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
55 	{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
56 	{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
57 	{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
58 	{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
59 	{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
60 	{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
61 	{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
62 };
63 
64 /*
65  * dpll locked at 1200 MHz - MPU clk at 600 MHz
66  * OMAP4430 OPP_NOM frequency
67  */
68 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
69 	{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
70 	{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
71 	{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
72 	{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
73 	{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
74 	{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
75 	{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
76 };
77 
78 /* OMAP4460 OPP_NOM frequency */
79 /* OMAP4470 OPP_NOM (Low Power) frequency */
80 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
81 	{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
82 	{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
83 	{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
84 	{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
85 	{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
86 	{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
87 	{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
88 };
89 
90 /* OMAP4430 ES1 OPP_NOM frequency */
91 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
92 	{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
93 	{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
94 	{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
95 	{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
96 	{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
97 	{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
98 	{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
99 };
100 
101 /* OMAP4430 ES2.X OPP_NOM frequency */
102 static const struct dpll_params
103 		core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
104 	{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 12 MHz   */
105 	{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 13 MHz   */
106 	{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 16.8 MHz */
107 	{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 19.2 MHz */
108 	{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 26 MHz   */
109 	{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1},	/* 27 MHz   */
110 	{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}	/* 38.4 MHz */
111 };
112 
113 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
114 	{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 12 MHz   */
115 	{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 13 MHz   */
116 	{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 16.8 MHz */
117 	{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 19.2 MHz */
118 	{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 26 MHz   */
119 	{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1},	/* 27 MHz   */
120 	{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}	/* 38.4 MHz */
121 };
122 
123 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
124 	{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
125 	{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
126 	{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
127 	{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
128 	{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
129 	{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
130 	{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
131 };
132 
133 /* ABE M & N values with sys_clk as source */
134 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
135 static const struct dpll_params
136 		abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
137 	{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 12 MHz   */
138 	{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
139 	{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
140 	{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
141 	{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
142 	{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
143 	{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
144 };
145 #else
146 /* ABE M & N values with 32K clock as source */
147 static const struct dpll_params abe_dpll_params_32k_196608khz = {
148 	750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
149 };
150 #endif
151 
152 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
153 	{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 12 MHz   */
154 	{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 13 MHz   */
155 	{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
156 	{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},		/* 19.2 MHz */
157 	{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 26 MHz   */
158 	{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1},	/* 27 MHz   */
159 	{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}		/* 38.4 MHz */
160 };
161 
162 struct dplls omap4430_dplls_es1 = {
163 	.mpu = mpu_dpll_params_1200mhz,
164 	.core = core_dpll_params_es1_1524mhz,
165 	.per = per_dpll_params_1536mhz,
166 	.iva = iva_dpll_params_1862mhz,
167 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
168 	.abe = abe_dpll_params_sysclk_196608khz,
169 #else
170 	.abe = &abe_dpll_params_32k_196608khz,
171 #endif
172 	.usb = usb_dpll_params_1920mhz,
173 	.ddr = NULL
174 };
175 
176 struct dplls omap4430_dplls_es20 = {
177 	.mpu = mpu_dpll_params_1200mhz,
178 	.core = core_dpll_params_es2_1600mhz_ddr200mhz,
179 	.per = per_dpll_params_1536mhz,
180 	.iva = iva_dpll_params_1862mhz,
181 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
182 	.abe = abe_dpll_params_sysclk_196608khz,
183 #else
184 	.abe = &abe_dpll_params_32k_196608khz,
185 #endif
186 	.usb = usb_dpll_params_1920mhz,
187 	.ddr = NULL
188 };
189 
190 struct dplls omap4430_dplls = {
191 	.mpu = mpu_dpll_params_1200mhz,
192 	.core = core_dpll_params_1600mhz,
193 	.per = per_dpll_params_1536mhz,
194 	.iva = iva_dpll_params_1862mhz,
195 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
196 	.abe = abe_dpll_params_sysclk_196608khz,
197 #else
198 	.abe = &abe_dpll_params_32k_196608khz,
199 #endif
200 	.usb = usb_dpll_params_1920mhz,
201 	.ddr = NULL
202 };
203 
204 struct dplls omap4460_dplls = {
205 	.mpu = mpu_dpll_params_1400mhz,
206 	.core = core_dpll_params_1600mhz,
207 	.per = per_dpll_params_1536mhz,
208 	.iva = iva_dpll_params_1862mhz,
209 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
210 	.abe = abe_dpll_params_sysclk_196608khz,
211 #else
212 	.abe = &abe_dpll_params_32k_196608khz,
213 #endif
214 	.usb = usb_dpll_params_1920mhz,
215 	.ddr = NULL
216 };
217 
218 struct dplls omap4470_dplls = {
219 	.mpu = mpu_dpll_params_1600mhz,
220 	.core = core_dpll_params_1600mhz,
221 	.per = per_dpll_params_1536mhz,
222 	.iva = iva_dpll_params_1862mhz,
223 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
224 	.abe = abe_dpll_params_sysclk_196608khz,
225 #else
226 	.abe = &abe_dpll_params_32k_196608khz,
227 #endif
228 	.usb = usb_dpll_params_1920mhz,
229 	.ddr = NULL
230 };
231 
232 struct pmic_data twl6030_4430es1 = {
233 	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV,
234 	.step = 12660, /* 12.66 mV represented in uV */
235 	/* The code starts at 1 not 0 */
236 	.start_code = 1,
237 	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
238 	.pmic_bus_init	= sri2c_init,
239 	.pmic_write	= omap_vc_bypass_send_value,
240 };
241 
242 /* twl6030 struct is used for TWL6030 and TWL6032 PMIC */
243 struct pmic_data twl6030 = {
244 	.base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV,
245 	.step = 12660, /* 12.66 mV represented in uV */
246 	/* The code starts at 1 not 0 */
247 	.start_code = 1,
248 	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
249 	.pmic_bus_init	= sri2c_init,
250 	.pmic_write	= omap_vc_bypass_send_value,
251 };
252 
253 struct pmic_data tps62361 = {
254 	.base_offset = TPS62361_BASE_VOLT_MV,
255 	.step = 10000, /* 10 mV represented in uV */
256 	.start_code = 0,
257 	.gpio = TPS62361_VSEL0_GPIO,
258 	.gpio_en = 1,
259 	.i2c_slave_addr	= SMPS_I2C_SLAVE_ADDR,
260 	.pmic_bus_init	= sri2c_init,
261 	.pmic_write	= omap_vc_bypass_send_value,
262 };
263 
264 struct vcores_data omap4430_volts_es1 = {
265 	.mpu.value[OPP_NOM] = 1325,
266 	.mpu.addr = SMPS_REG_ADDR_VCORE1,
267 	.mpu.pmic = &twl6030_4430es1,
268 
269 	.core.value[OPP_NOM] = 1200,
270 	.core.addr = SMPS_REG_ADDR_VCORE3,
271 	.core.pmic = &twl6030_4430es1,
272 
273 	.mm.value[OPP_NOM] = 1200,
274 	.mm.addr = SMPS_REG_ADDR_VCORE2,
275 	.mm.pmic = &twl6030_4430es1,
276 };
277 
278 struct vcores_data omap4430_volts = {
279 	.mpu.value[OPP_NOM] = 1325,
280 	.mpu.addr = SMPS_REG_ADDR_VCORE1,
281 	.mpu.pmic = &twl6030,
282 
283 	.core.value[OPP_NOM] = 1200,
284 	.core.addr = SMPS_REG_ADDR_VCORE3,
285 	.core.pmic = &twl6030,
286 
287 	.mm.value[OPP_NOM] = 1200,
288 	.mm.addr = SMPS_REG_ADDR_VCORE2,
289 	.mm.pmic = &twl6030,
290 };
291 
292 struct vcores_data omap4460_volts = {
293 	.mpu.value[OPP_NOM] = 1203,
294 	.mpu.addr = TPS62361_REG_ADDR_SET1,
295 	.mpu.pmic = &tps62361,
296 
297 	.core.value[OPP_NOM] = 1200,
298 	.core.addr = SMPS_REG_ADDR_VCORE1,
299 	.core.pmic = &twl6030,
300 
301 	.mm.value[OPP_NOM] = 1200,
302 	.mm.addr = SMPS_REG_ADDR_VCORE2,
303 	.mm.pmic = &twl6030,
304 };
305 
306 /*
307  * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
308  * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
309  */
310 struct vcores_data omap4470_volts = {
311 	.mpu.value[OPP_NOM] = 1202,
312 	.mpu.addr = SMPS_REG_ADDR_SMPS1,
313 	.mpu.pmic = &twl6030,
314 
315 	.core.value[OPP_NOM] = 1126,
316 	.core.addr = SMPS_REG_ADDR_SMPS2,
317 	.core.pmic = &twl6030,
318 
319 	.mm.value[OPP_NOM] = 1139,
320 	.mm.addr = SMPS_REG_ADDR_SMPS5,
321 	.mm.pmic = &twl6030,
322 };
323 
324 /*
325  * Enable essential clock domains, modules and
326  * do some additional special settings needed
327  */
328 void enable_basic_clocks(void)
329 {
330 	u32 const clk_domains_essential[] = {
331 		(*prcm)->cm_l4per_clkstctrl,
332 		(*prcm)->cm_l3init_clkstctrl,
333 		(*prcm)->cm_memif_clkstctrl,
334 		(*prcm)->cm_l4cfg_clkstctrl,
335 		0
336 	};
337 
338 	u32 const clk_modules_hw_auto_essential[] = {
339 		(*prcm)->cm_l3_gpmc_clkctrl,
340 		(*prcm)->cm_memif_emif_1_clkctrl,
341 		(*prcm)->cm_memif_emif_2_clkctrl,
342 		(*prcm)->cm_l4cfg_l4_cfg_clkctrl,
343 		(*prcm)->cm_wkup_gpio1_clkctrl,
344 		(*prcm)->cm_l4per_gpio2_clkctrl,
345 		(*prcm)->cm_l4per_gpio3_clkctrl,
346 		(*prcm)->cm_l4per_gpio4_clkctrl,
347 		(*prcm)->cm_l4per_gpio5_clkctrl,
348 		(*prcm)->cm_l4per_gpio6_clkctrl,
349 		0
350 	};
351 
352 	u32 const clk_modules_explicit_en_essential[] = {
353 		(*prcm)->cm_wkup_gptimer1_clkctrl,
354 		(*prcm)->cm_l3init_hsmmc1_clkctrl,
355 		(*prcm)->cm_l3init_hsmmc2_clkctrl,
356 		(*prcm)->cm_l4per_gptimer2_clkctrl,
357 		(*prcm)->cm_wkup_wdtimer2_clkctrl,
358 		(*prcm)->cm_l4per_uart3_clkctrl,
359 		(*prcm)->cm_l4per_i2c1_clkctrl,
360 		(*prcm)->cm_l4per_i2c2_clkctrl,
361 		(*prcm)->cm_l4per_i2c3_clkctrl,
362 		(*prcm)->cm_l4per_i2c4_clkctrl,
363 		0
364 	};
365 
366 	/* Enable optional additional functional clock for GPIO4 */
367 	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
368 			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
369 
370 	/* Enable 96 MHz clock for MMC1 & MMC2 */
371 	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
372 			HSMMC_CLKCTRL_CLKSEL_MASK);
373 	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
374 			HSMMC_CLKCTRL_CLKSEL_MASK);
375 
376 	/* Select 32KHz clock as the source of GPTIMER1 */
377 	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
378 			GPTIMER1_CLKCTRL_CLKSEL_MASK);
379 
380 	/* Enable optional 48M functional clock for USB PHY */
381 	setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl,
382 			USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
383 
384 	/* Enable 32 KHz clock for USB PHY */
385 	setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
386 			USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
387 
388 	do_enable_clocks(clk_domains_essential,
389 			 clk_modules_hw_auto_essential,
390 			 clk_modules_explicit_en_essential,
391 			 1);
392 }
393 
394 void enable_basic_uboot_clocks(void)
395 {
396 	u32 const clk_domains_essential[] = {
397 		0
398 	};
399 
400 	u32 const clk_modules_hw_auto_essential[] = {
401 		(*prcm)->cm_l3init_hsusbotg_clkctrl,
402 		(*prcm)->cm_l3init_usbphy_clkctrl,
403 		(*prcm)->cm_clksel_usb_60mhz,
404 		(*prcm)->cm_l3init_hsusbtll_clkctrl,
405 		0
406 	};
407 
408 	u32 const clk_modules_explicit_en_essential[] = {
409 		(*prcm)->cm_l4per_mcspi1_clkctrl,
410 		(*prcm)->cm_l3init_hsusbhost_clkctrl,
411 		0
412 	};
413 
414 	do_enable_clocks(clk_domains_essential,
415 			 clk_modules_hw_auto_essential,
416 			 clk_modules_explicit_en_essential,
417 			 1);
418 }
419 
420 void hw_data_init(void)
421 {
422 	u32 omap_rev = omap_revision();
423 
424 	(*prcm) = &omap4_prcm;
425 
426 	switch (omap_rev) {
427 
428 	case OMAP4430_ES1_0:
429 	*dplls_data = &omap4430_dplls_es1;
430 	*omap_vcores = &omap4430_volts_es1;
431 	break;
432 
433 	case OMAP4430_ES2_0:
434 	*dplls_data = &omap4430_dplls_es20;
435 	*omap_vcores = &omap4430_volts;
436 	break;
437 
438 	case OMAP4430_ES2_1:
439 	case OMAP4430_ES2_2:
440 	case OMAP4430_ES2_3:
441 	*dplls_data = &omap4430_dplls;
442 	*omap_vcores = &omap4430_volts;
443 	break;
444 
445 	case OMAP4460_ES1_0:
446 	case OMAP4460_ES1_1:
447 	*dplls_data = &omap4460_dplls;
448 	*omap_vcores = &omap4460_volts;
449 	break;
450 
451 	case OMAP4470_ES1_0:
452 	*dplls_data = &omap4470_dplls;
453 	*omap_vcores = &omap4470_volts;
454 	break;
455 
456 	default:
457 		printf("\n INVALID OMAP REVISION ");
458 	}
459 
460 	*ctrl = &omap4_ctrl;
461 }
462