1 /* 2 * 3 * HW data initialization for OMAP4 4 * 5 * (C) Copyright 2013 6 * Texas Instruments, <www.ti.com> 7 * 8 * Sricharan R <r.sricharan@ti.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 #include <common.h> 13 #include <asm/arch/omap.h> 14 #include <asm/arch/sys_proto.h> 15 #include <asm/omap_common.h> 16 #include <asm/arch/clock.h> 17 #include <asm/omap_gpio.h> 18 #include <asm/io.h> 19 20 struct prcm_regs const **prcm = 21 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR; 22 struct dplls const **dplls_data = 23 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR; 24 struct vcores_data const **omap_vcores = 25 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR; 26 struct omap_sys_ctrl_regs const **ctrl = 27 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL; 28 29 /* 30 * The M & N values in the following tables are created using the 31 * following tool: 32 * tools/omap/clocks_get_m_n.c 33 * Please use this tool for creating the table for any new frequency. 34 */ 35 36 /* 37 * dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF 38 * OMAP4460 OPP_NOM frequency 39 */ 40 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { 41 {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 42 {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 43 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 44 {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 45 {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 46 {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 47 {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 48 }; 49 50 /* 51 * dpll locked at 1600 MHz - MPU clk at 800 MHz(OPP Turbo 4430) 52 * OMAP4430 OPP_TURBO frequency 53 * OMAP4470 OPP_NOM frequency 54 */ 55 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { 56 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 57 {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 58 {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 59 {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 60 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 61 {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 62 {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 63 }; 64 65 /* 66 * dpll locked at 1200 MHz - MPU clk at 600 MHz 67 * OMAP4430 OPP_NOM frequency 68 */ 69 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { 70 {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 71 {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 72 {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 73 {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 74 {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 75 {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 76 {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 77 }; 78 79 /* OMAP4460 OPP_NOM frequency */ 80 /* OMAP4470 OPP_NOM (Low Power) frequency */ 81 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { 82 {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ 83 {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ 84 {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ 85 {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 86 {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ 87 {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ 88 {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ 89 }; 90 91 /* OMAP4430 ES1 OPP_NOM frequency */ 92 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { 93 {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ 94 {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ 95 {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ 96 {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 97 {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ 98 {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ 99 {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ 100 }; 101 102 /* OMAP4430 ES2.X OPP_NOM frequency */ 103 static const struct dpll_params 104 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { 105 {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ 106 {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ 107 {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ 108 {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 109 {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ 110 {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ 111 {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ 112 }; 113 114 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { 115 {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ 116 {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ 117 {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ 118 {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ 119 {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ 120 {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ 121 {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ 122 }; 123 124 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { 125 {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 126 {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 127 {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 128 {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 129 {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 130 {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 131 {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 132 }; 133 134 /* ABE M & N values with sys_clk as source */ 135 static const struct dpll_params 136 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { 137 {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 138 {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 139 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 140 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 141 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 142 {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 143 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 144 }; 145 146 /* ABE M & N values with 32K clock as source */ 147 static const struct dpll_params abe_dpll_params_32k_196608khz = { 148 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 149 }; 150 151 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { 152 {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ 153 {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ 154 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ 155 {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ 156 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ 157 {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ 158 {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ 159 }; 160 161 struct dplls omap4430_dplls_es1 = { 162 .mpu = mpu_dpll_params_1200mhz, 163 .core = core_dpll_params_es1_1524mhz, 164 .per = per_dpll_params_1536mhz, 165 .iva = iva_dpll_params_1862mhz, 166 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 167 .abe = abe_dpll_params_sysclk_196608khz, 168 #else 169 .abe = &abe_dpll_params_32k_196608khz, 170 #endif 171 .usb = usb_dpll_params_1920mhz, 172 .ddr = NULL 173 }; 174 175 struct dplls omap4430_dplls_es20 = { 176 .mpu = mpu_dpll_params_1200mhz, 177 .core = core_dpll_params_es2_1600mhz_ddr200mhz, 178 .per = per_dpll_params_1536mhz, 179 .iva = iva_dpll_params_1862mhz, 180 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 181 .abe = abe_dpll_params_sysclk_196608khz, 182 #else 183 .abe = &abe_dpll_params_32k_196608khz, 184 #endif 185 .usb = usb_dpll_params_1920mhz, 186 .ddr = NULL 187 }; 188 189 struct dplls omap4430_dplls = { 190 .mpu = mpu_dpll_params_1200mhz, 191 .core = core_dpll_params_1600mhz, 192 .per = per_dpll_params_1536mhz, 193 .iva = iva_dpll_params_1862mhz, 194 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 195 .abe = abe_dpll_params_sysclk_196608khz, 196 #else 197 .abe = &abe_dpll_params_32k_196608khz, 198 #endif 199 .usb = usb_dpll_params_1920mhz, 200 .ddr = NULL 201 }; 202 203 struct dplls omap4460_dplls = { 204 .mpu = mpu_dpll_params_1400mhz, 205 .core = core_dpll_params_1600mhz, 206 .per = per_dpll_params_1536mhz, 207 .iva = iva_dpll_params_1862mhz, 208 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 209 .abe = abe_dpll_params_sysclk_196608khz, 210 #else 211 .abe = &abe_dpll_params_32k_196608khz, 212 #endif 213 .usb = usb_dpll_params_1920mhz, 214 .ddr = NULL 215 }; 216 217 struct dplls omap4470_dplls = { 218 .mpu = mpu_dpll_params_1600mhz, 219 .core = core_dpll_params_1600mhz, 220 .per = per_dpll_params_1536mhz, 221 .iva = iva_dpll_params_1862mhz, 222 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK 223 .abe = abe_dpll_params_sysclk_196608khz, 224 #else 225 .abe = &abe_dpll_params_32k_196608khz, 226 #endif 227 .usb = usb_dpll_params_1920mhz, 228 .ddr = NULL 229 }; 230 231 struct pmic_data twl6030_4430es1 = { 232 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, 233 .step = 12660, /* 12.66 mV represented in uV */ 234 /* The code starts at 1 not 0 */ 235 .start_code = 1, 236 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, 237 .pmic_bus_init = sri2c_init, 238 .pmic_write = omap_vc_bypass_send_value, 239 }; 240 241 /* twl6030 struct is used for TWL6030 and TWL6032 PMIC */ 242 struct pmic_data twl6030 = { 243 .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, 244 .step = 12660, /* 12.66 mV represented in uV */ 245 /* The code starts at 1 not 0 */ 246 .start_code = 1, 247 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, 248 .pmic_bus_init = sri2c_init, 249 .pmic_write = omap_vc_bypass_send_value, 250 }; 251 252 struct pmic_data tps62361 = { 253 .base_offset = TPS62361_BASE_VOLT_MV, 254 .step = 10000, /* 10 mV represented in uV */ 255 .start_code = 0, 256 .gpio = TPS62361_VSEL0_GPIO, 257 .gpio_en = 1, 258 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, 259 .pmic_bus_init = sri2c_init, 260 .pmic_write = omap_vc_bypass_send_value, 261 }; 262 263 struct vcores_data omap4430_volts_es1 = { 264 .mpu.value = 1325, 265 .mpu.addr = SMPS_REG_ADDR_VCORE1, 266 .mpu.pmic = &twl6030_4430es1, 267 268 .core.value = 1200, 269 .core.addr = SMPS_REG_ADDR_VCORE3, 270 .core.pmic = &twl6030_4430es1, 271 272 .mm.value = 1200, 273 .mm.addr = SMPS_REG_ADDR_VCORE2, 274 .mm.pmic = &twl6030_4430es1, 275 }; 276 277 struct vcores_data omap4430_volts = { 278 .mpu.value = 1325, 279 .mpu.addr = SMPS_REG_ADDR_VCORE1, 280 .mpu.pmic = &twl6030, 281 282 .core.value = 1200, 283 .core.addr = SMPS_REG_ADDR_VCORE3, 284 .core.pmic = &twl6030, 285 286 .mm.value = 1200, 287 .mm.addr = SMPS_REG_ADDR_VCORE2, 288 .mm.pmic = &twl6030, 289 }; 290 291 struct vcores_data omap4460_volts = { 292 .mpu.value = 1203, 293 .mpu.addr = TPS62361_REG_ADDR_SET1, 294 .mpu.pmic = &tps62361, 295 296 .core.value = 1200, 297 .core.addr = SMPS_REG_ADDR_VCORE1, 298 .core.pmic = &twl6030, 299 300 .mm.value = 1200, 301 .mm.addr = SMPS_REG_ADDR_VCORE2, 302 .mm.pmic = &twl6030, 303 }; 304 305 /* 306 * Take closest integer part of the mV value corresponding to a TWL6032 SMPS 307 * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7. 308 */ 309 struct vcores_data omap4470_volts = { 310 .mpu.value = 1202, 311 .mpu.addr = SMPS_REG_ADDR_SMPS1, 312 .mpu.pmic = &twl6030, 313 314 .core.value = 1126, 315 .core.addr = SMPS_REG_ADDR_SMPS2, 316 .core.pmic = &twl6030, 317 318 .mm.value = 1139, 319 .mm.addr = SMPS_REG_ADDR_SMPS5, 320 .mm.pmic = &twl6030, 321 }; 322 323 /* 324 * Enable essential clock domains, modules and 325 * do some additional special settings needed 326 */ 327 void enable_basic_clocks(void) 328 { 329 u32 const clk_domains_essential[] = { 330 (*prcm)->cm_l4per_clkstctrl, 331 (*prcm)->cm_l3init_clkstctrl, 332 (*prcm)->cm_memif_clkstctrl, 333 (*prcm)->cm_l4cfg_clkstctrl, 334 0 335 }; 336 337 u32 const clk_modules_hw_auto_essential[] = { 338 (*prcm)->cm_l3_gpmc_clkctrl, 339 (*prcm)->cm_memif_emif_1_clkctrl, 340 (*prcm)->cm_memif_emif_2_clkctrl, 341 (*prcm)->cm_l4cfg_l4_cfg_clkctrl, 342 (*prcm)->cm_wkup_gpio1_clkctrl, 343 (*prcm)->cm_l4per_gpio2_clkctrl, 344 (*prcm)->cm_l4per_gpio3_clkctrl, 345 (*prcm)->cm_l4per_gpio4_clkctrl, 346 (*prcm)->cm_l4per_gpio5_clkctrl, 347 (*prcm)->cm_l4per_gpio6_clkctrl, 348 0 349 }; 350 351 u32 const clk_modules_explicit_en_essential[] = { 352 (*prcm)->cm_wkup_gptimer1_clkctrl, 353 (*prcm)->cm_l3init_hsmmc1_clkctrl, 354 (*prcm)->cm_l3init_hsmmc2_clkctrl, 355 (*prcm)->cm_l4per_gptimer2_clkctrl, 356 (*prcm)->cm_wkup_wdtimer2_clkctrl, 357 (*prcm)->cm_l4per_uart3_clkctrl, 358 (*prcm)->cm_l4per_i2c1_clkctrl, 359 (*prcm)->cm_l4per_i2c2_clkctrl, 360 (*prcm)->cm_l4per_i2c3_clkctrl, 361 (*prcm)->cm_l4per_i2c4_clkctrl, 362 0 363 }; 364 365 /* Enable optional additional functional clock for GPIO4 */ 366 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, 367 GPIO4_CLKCTRL_OPTFCLKEN_MASK); 368 369 /* Enable 96 MHz clock for MMC1 & MMC2 */ 370 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, 371 HSMMC_CLKCTRL_CLKSEL_MASK); 372 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, 373 HSMMC_CLKCTRL_CLKSEL_MASK); 374 375 /* Select 32KHz clock as the source of GPTIMER1 */ 376 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, 377 GPTIMER1_CLKCTRL_CLKSEL_MASK); 378 379 /* Enable optional 48M functional clock for USB PHY */ 380 setbits_le32((*prcm)->cm_l3init_usbphy_clkctrl, 381 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK); 382 383 /* Enable 32 KHz clock for USB PHY */ 384 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, 385 USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K); 386 387 do_enable_clocks(clk_domains_essential, 388 clk_modules_hw_auto_essential, 389 clk_modules_explicit_en_essential, 390 1); 391 } 392 393 void enable_basic_uboot_clocks(void) 394 { 395 u32 const clk_domains_essential[] = { 396 0 397 }; 398 399 u32 const clk_modules_hw_auto_essential[] = { 400 (*prcm)->cm_l3init_hsusbotg_clkctrl, 401 (*prcm)->cm_l3init_usbphy_clkctrl, 402 (*prcm)->cm_clksel_usb_60mhz, 403 (*prcm)->cm_l3init_hsusbtll_clkctrl, 404 0 405 }; 406 407 u32 const clk_modules_explicit_en_essential[] = { 408 (*prcm)->cm_l4per_mcspi1_clkctrl, 409 (*prcm)->cm_l3init_hsusbhost_clkctrl, 410 0 411 }; 412 413 do_enable_clocks(clk_domains_essential, 414 clk_modules_hw_auto_essential, 415 clk_modules_explicit_en_essential, 416 1); 417 } 418 419 void hw_data_init(void) 420 { 421 u32 omap_rev = omap_revision(); 422 423 (*prcm) = &omap4_prcm; 424 425 switch (omap_rev) { 426 427 case OMAP4430_ES1_0: 428 *dplls_data = &omap4430_dplls_es1; 429 *omap_vcores = &omap4430_volts_es1; 430 break; 431 432 case OMAP4430_ES2_0: 433 *dplls_data = &omap4430_dplls_es20; 434 *omap_vcores = &omap4430_volts; 435 break; 436 437 case OMAP4430_ES2_1: 438 case OMAP4430_ES2_2: 439 case OMAP4430_ES2_3: 440 *dplls_data = &omap4430_dplls; 441 *omap_vcores = &omap4430_volts; 442 break; 443 444 case OMAP4460_ES1_0: 445 case OMAP4460_ES1_1: 446 *dplls_data = &omap4460_dplls; 447 *omap_vcores = &omap4460_volts; 448 break; 449 450 case OMAP4470_ES1_0: 451 *dplls_data = &omap4470_dplls; 452 *omap_vcores = &omap4470_volts; 453 break; 454 455 default: 456 printf("\n INVALID OMAP REVISION "); 457 } 458 459 *ctrl = &omap4_ctrl; 460 } 461