1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * EMIF programming 4 * 5 * (C) Copyright 2010 6 * Texas Instruments, <www.ti.com> 7 * 8 * Aneesh V <aneesh@ti.com> 9 */ 10 11 #include <common.h> 12 #include <asm/emif.h> 13 #include <asm/arch/sys_proto.h> 14 #include <asm/utils.h> 15 16 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 17 u32 *const T_num = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_NUM; 18 u32 *const T_den = (u32 *)OMAP_SRAM_SCRATCH_EMIF_T_DEN; 19 #endif 20 21 #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS 22 /* Base AC Timing values specified by JESD209-2 for 400MHz operation */ 23 static const struct lpddr2_ac_timings timings_jedec_400_mhz = { 24 .max_freq = 400000000, 25 .RL = 6, 26 .tRPab = 21, 27 .tRCD = 18, 28 .tWR = 15, 29 .tRASmin = 42, 30 .tRRD = 10, 31 .tWTRx2 = 15, 32 .tXSR = 140, 33 .tXPx2 = 15, 34 .tRFCab = 130, 35 .tRTPx2 = 15, 36 .tCKE = 3, 37 .tCKESR = 15, 38 .tZQCS = 90, 39 .tZQCL = 360, 40 .tZQINIT = 1000, 41 .tDQSCKMAXx2 = 11, 42 .tRASmax = 70, 43 .tFAW = 50 44 }; 45 46 /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */ 47 static const struct lpddr2_ac_timings timings_jedec_200_mhz = { 48 .max_freq = 200000000, 49 .RL = 3, 50 .tRPab = 21, 51 .tRCD = 18, 52 .tWR = 15, 53 .tRASmin = 42, 54 .tRRD = 10, 55 .tWTRx2 = 20, 56 .tXSR = 140, 57 .tXPx2 = 15, 58 .tRFCab = 130, 59 .tRTPx2 = 15, 60 .tCKE = 3, 61 .tCKESR = 15, 62 .tZQCS = 90, 63 .tZQCL = 360, 64 .tZQINIT = 1000, 65 .tDQSCKMAXx2 = 11, 66 .tRASmax = 70, 67 .tFAW = 50 68 }; 69 70 /* 71 * Min tCK values specified by JESD209-2 72 * Min tCK specifies the minimum duration of some AC timing parameters in terms 73 * of the number of cycles. If the calculated number of cycles based on the 74 * absolute time value is less than the min tCK value, min tCK value should 75 * be used instead. This typically happens at low frequencies. 76 */ 77 static const struct lpddr2_min_tck min_tck_jedec = { 78 .tRL = 3, 79 .tRP_AB = 3, 80 .tRCD = 3, 81 .tWR = 3, 82 .tRAS_MIN = 3, 83 .tRRD = 2, 84 .tWTR = 2, 85 .tXP = 2, 86 .tRTP = 2, 87 .tCKE = 3, 88 .tCKESR = 3, 89 .tFAW = 8 90 }; 91 92 static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = { 93 &timings_jedec_200_mhz, 94 &timings_jedec_400_mhz 95 }; 96 97 const struct lpddr2_device_timings jedec_default_timings = { 98 .ac_timings = jedec_ac_timings, 99 .min_tck = &min_tck_jedec 100 }; 101 102 void emif_get_device_timings(u32 emif_nr, 103 const struct lpddr2_device_timings **cs0_device_timings, 104 const struct lpddr2_device_timings **cs1_device_timings) 105 { 106 /* Assume Identical devices on EMIF1 & EMIF2 */ 107 *cs0_device_timings = &jedec_default_timings; 108 *cs1_device_timings = &jedec_default_timings; 109 } 110 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */ 111